An electronic circuit according to an embodiment includes a clock generator, a delay element, a first electromagnetic coupler, a first frequency converter, a second electromagnetic coupler, a second frequency converter, a controller and an output device. The clock generator is configured to generate a first clock signal. The delay element is configured to output a second clock signal which has a phase delayed with respect to the first clock signal. The first electromagnetic coupler is configured to transmit one of the first and second clock signals by electromagnetic coupling. The first frequency converter is driven by the one of the first and second clock signals transmitted from the first electromagnetic coupler and is configured to convert a first input signal to a first signal with a first frequency corresponding to the one of the first and second clock signals.

An electronic circuit according to an embodiment includes a clock generator, a delay element, a first electromagnetic coupler, a first frequency converter, a second electromagnetic coupler, a second frequency converter, a controller and an output device. The clock generator is configured to generate a first clock signal. The delay element is configured to output a second clock signal which has a phase delayed with respect to the first clock signal. The first electromagnetic coupler is configured to transmit one of the first and second clock signals by electromagnetic coupling. The first frequency converter is driven by the one of the first and second clock signals transmitted from the first electromagnetic coupler and is configured to convert a first input signal to a first signal with a first frequency corresponding to the one of the first and second clock signals.

Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.

An impulse voltage generation device comprises: a high voltage generator to generate high DC voltage; a capacitor that is disposed in parallel to the high voltage generator and can be charged to a high voltage state; a power semiconductor switch that is placed at an output side of the high voltage generator and in series to the high voltage generator and is designed to shut off or allow electricity output from the high voltage generator; a function generator to output changes over time of impulse voltage to be applied to the test target; a current detector to detect output current; and an overcurrent protection circuit that is configured to conduct analog-to-digital conversion at sampling intervals sufficiently shorter than the application intervals when receiving a current signal from the current detector, monitors values of the output current, and to block output from the function generator to the power semiconductor switch if it is determined that there is an abnormality.

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

A circuit for generating a time delay, including a capacitive element for integrating a first current supplied by a first current source, in which the first current source includes a switched-capacitor circuit.

According to one embodiment of an asynchronous communication device, the transmitter circuit includes a signal generation circuit to output a first pulse signal and a delay compensation circuit to receive the first pulse signal, perform delay compensation processing on the pulse width of the first pulse signal, and output a second pulse signal obtained by the delay compensation processing. The delay unit receives the second pulse signal, causes delay in the rising or falling edge of the second pulse signal, and outputs a third pulse signal in which the delay is caused. The receiver circuit receives the third pulse signal and performs signal processing based on the third pulse signal. The delay compensation circuit, while maintaining the pulse period of the first pulse signal, performs pre-compensation processing on the first pulse signal based on a delay value of the delay to be caused by the delay unit.

A method for controlling a load-current zero-crossing of a switching regulator having a high-side switch and a low-side switch includes detecting, by a spike detection circuit, a presence of a spike on an output voltage of the switching regulator, determining, by the spike detection circuit, in the event that a spike is present, whether the spike is a positive spike or a negative spike, and adjusting a turn-off timing of the low-side switch based on a determination result.

A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.