A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.

Switch comprising at least one PCM portion that can be in a conducting or blocked state depending on the amorphous or crystalline state of the PCM that can change state when it is heated, in which the PCM portion is continuous and has an elongated shape such that an input and an output of the switch are connected to two ends of the PCM portion respectively that are separated from each other by a distance corresponding to the largest dimension of the PCM portion, and comprising a control device of the state of the switch capable of passing heating currents through the PCM portion, approximately perpendicular to the largest dimension of the PCM portion, from at least two input points separated from each other and separated from the ends of the PCM portion, to at least two output points separated from each other and separated from the ends of the PCM portion.

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

According to one embodiment, an analog-to-digital converter includes: a digital-to-analog converter configured to generate an analog voltage based on a sampled analog signal and a digital code; a clock generator configured to generate a first clock signal; a comparator configured to receive the analog voltage from the digital-to-analog converter, and perform digital output based on the first clock signal; and a controller configured to generate the digital code based on the digital output of the comparator. The clock generator varies a delay period, which is from the end of sampling of the analog signal to the start of generating the first clock signal, for each sampling of the analog signal.

According to one embodiment, an analog-to-digital converter includes: a digital-to-analog converter configured to generate an analog voltage based on a sampled analog signal and a digital code; a clock generator configured to generate a first clock signal; a comparator configured to receive the analog voltage from the digital-to-analog converter, and perform digital output based on the first clock signal; and a controller configured to generate the digital code based on the digital output of the comparator. The clock generator varies a delay period, which is from the end of sampling of the analog signal to the start of generating the first clock signal, for each sampling of the analog signal.

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

Switch comprising at least one PCM portion that can be in a conducting or blocked state depending on the amorphous or crystalline state of the PCM that can change state when it is heated, in which the PCM portion is continuous and has an elongated shape such that an input and an output of the switch are connected to two ends of the PCM portion respectively that are separated from each other by a distance corresponding to the largest dimension of the PCM portion, and comprising a control device of the state of the switch capable of passing heating currents through the PCM portion, approximately perpendicular to the largest dimension of the PCM portion, from at least two input points separated from each other and separated from the ends of the PCM portion, to at least two output points separated from each other and separated from the ends of the PCM portion.

Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit generally includes a first clock-generation stage comprising first cascode-connected transistors the first cascode-connected transistors having gates coupled to a first input clock node. The multi-stage clock generation circuit may also include a second clock-generation stage comprising second cascode-connected transistors, the second cascode-connected transistors having gates coupled to a second input clock node. A first transistor may be coupled to the second cascode-connected transistors, the first transistor having a gate coupled to drains of the first cascode-connected transistors.

The disclosure relates to a method for operating a pulse generator for generating measuring pulses for a capacitive sensor having an adjustable pulse time in the range from 10 ns to 200 ns, having a controllable delay circuit which contains a first integrating RC combination (RT1/CT1) and a second integrating RC combination (RT2/CT2), having a logical combining element having two inputs and one output, an initialization circuit and a control unit, wherein the first input of the logical combining element receives a clock signal, and the second input of the logical combining element receives an analog setting signal (SSE) from the output of the delay circuit, wherein two simultaneous clock signals are generated, of which the first clock signal (T) is led without delay to the first input of the logical combining element, and the second clock signal (T2), delayed by the delay circuit, is led to the second input of the logical combining element, time-variable output pulses are generated with the aid of time-variable preloading signals (VL), wherein the output from the delay circuit after each measuring pulse is discharged or charged by the initialization switch.

A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.