Disclosed are a method and an apparatus of digital feedback based adaptive delay time control for a high efficiency active rectifier. According to the present invention, provided is an apparatus for digital feedback based adaptive delay time control, which adaptively compensates a driving delay of a switch by controlling a time of a delay circuit through a digital feedback-based compensation technique, and operate the switch at an appropriate timing in spite of changes in operation environments such as an input voltage and a load to increase the efficiency of an AC-DC rectifier.

Delay circuitry includes a temperature compensation control circuit and a delay circuit. The temperature compensation control circuit is configured to generate a target temperature compensation control signal based on an initial control signal, a real-time ambient temperature signal, a temperature coefficient compensation enable signal, and a temperature coefficient control signal. The delay circuit is connected to the temperature compensation control circuit, and is configured to generate a temperature compensated target delay signal based on the target temperature compensation control signal and an initial delay signal such that a delay time of the target delay signal generated by the delay circuit can be dynamically compensated based on a real-time ambient temperature signal collected by a temperature sensor.

A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

The present invention provides a system including a transmitter and a receiver is disclosed. The transmitter includes a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced. The receiver includes a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively.

Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.

A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.

A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node. The apparatus additionally includes an interpolation circuit configured to weight the second interpolation signal based on a weighting factor, and to combine the first interpolation signal and the weighted second interpolation signal to generate a third interpolation signal.