An apparatus for clock deskew includes: a first delay element configured to receive a clock signal from a clock, wherein the delay element comprises multiple delay lines; a first multiplexer coupled to the multiple delay lines; a sensor configured to sense a voltage, a temperature, or both, and to provide a sensor output based at least on the sensed voltage and/or the sensed temperature; and a converter configured to receive the sensor output, and to generate a converted signal; wherein the first multiplexer is configured to provide a delay line output from one of the multiple delay lines based at least in part on the converted signal.

A system-on-chip (SOC) includes a compensation circuit that compensates for PVT variations of the SoC and an external memory connected to the SOC. The compensation circuit includes first through third delay calculators, first through third delay circuits, first through third latches, first and second comparators, and a delay control circuit. The delay calculators generate first through third delay count data. The delay circuits use three delay counts to generate first through third clock signals. The latches receive data stored in the external memory, and output start-point, mid-point, and end-point data, respectively. The first and second comparators generate increment or decrement signals based on the start-point, mid-point and end-point data comparisons. The delay control circuit generates modified first delay count data, which along with the first through third delay count data, compensate for the PVT variations of the SoC and the external memory.

Provided is a semiconductor device including a target circuit, a monitoring circuit, and a voltage controller. The target circuit includes a transistor. The monitoring circuit is configured to measure a temperature of the target circuit or measure a delay time between an input and an output of the target circuit. The voltage controller is configured to adjust a driving voltage for driving the target circuit or a back-bias voltage for adjusting a threshold voltage of the transistor by referring to at least one of the temperature and the delay time. As the temperature increases, the delay time decreases.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

A method for transmitting data in a direction of transmission of a clock signal, wherein positive and negative edges of the clock signal are transmitted by pulses with opposite polarity, wherein the polarity of the pulses is not inverted when no data is transmitted, and wherein the polarity of at least one pulse is inverted when data is transmitted.

Temperature, process and supply compensated delay circuits, DC to DC converters and integrated circuits are presented in which switch driver dead time delays are provided using a plurality of cascaded CMOS inverter circuits with a first inverter coupled through a diode-connected MOS transistor to a regulated voltage or circuit ground and a MOS capacitor is provided between the first inverter output and the regulated voltage or circuit ground to provide a controlled delay time. A second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator, and certain embodiments include one or more intermediate CMOS inverters to form a level shifting circuit between the second inverter and the final output inverter, with the level shift inverters powered by successively higher compensated voltages that decrease with increasing temperature.

The present disclosure discloses an oscillating circuit having a temperature compensation mechanism. A NAND gate receives an input signal transiting from a low state level to a maintaining high state to initialize an oscillating behavior and a delayed control signal to generate an output oscillating signal. A first inverter having a negative temperature coefficient resistance inverts the output oscillating signal to generate an inverted output oscillating signal to be received and delayed by a RC delay circuit, including an oscillating resistor having a positive temperature coefficient resistance and an oscillating capacitor to generate a delayed and inverted control signal. A second inverter inverts the delayed and inverted control signal to generate a delayed control signal. A third inverter inverts the output oscillating signal to generate a final oscillating signal. The negative temperature coefficient resistance and the positive temperature coefficient resistance together determine an oscillating circuit temperature coefficient.