A delay cell includes: a plurality of delay elements coupled in series; and at least one three-phase inverter that is coupled in parallel to at least one of the delay elements, and that receives through a first control terminal a first bias voltage for compensating for a variation of a power source voltage, and receives through a second control terminal a second bias voltage for compensating for a variation of a ground voltage.

An optical receiver includes a transimpedance amplifier that converts a current signal corresponding to an optical signal into a voltage signal. The transimpedance amplifier includes an input terminal receiving the current signal, an output terminal outputting the voltage signal, an inverting circuit including a pull-up device that pull-up drives the voltage signal of the output terminal according to the current signal, and a pull-down device that pull-down drives the voltage signal of the output terminal according to the current signal, a feedback resistor electrically connected between the input and output terminals, a first resistor electrically connected between the input terminal and the pull-up device, and a second resistor electrically connected between the input terminal and the pull-down device.

A delay cell includes: a plurality of delay elements coupled in series; and at least one three-phase inverter that is coupled in parallel to at least one of the delay elements, and that receives through a first control terminal a first bias voltage for compensating for a variation of a power source voltage, and receives through a second control terminal a second bias voltage for compensating for a variation of a ground voltage.

A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

An optical receiver includes a transimpedance amplifier that converts a current signal corresponding to an optical signal into a voltage signal. The transimpedance amplifier includes an input terminal receiving the current signal, an output terminal outputting the voltage signal, an inverting circuit including a pull-up device that pull-up drives the voltage signal of the output terminal according to the current signal, and a pull-down device that pull-down drives the voltage signal of the output terminal according to the current signal, a feedback resistor electrically connected between the input and output terminals, a first resistor electrically connected between the input terminal and the pull-up device, and a second resistor electrically connected between the input terminal and the pull-down device.

In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.

In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.

A time-to-digital converter (TDC, 110) obtains a Start signal to indicate the start of an event, and a Stop signal whose assertion indicates the stop of the event. The Stop signal can be asserted multiple times due to false indications of the event stop. The TDC continuously monitors the Stop signal to generate a separate digital value (T.j_i) for the duration from the event's starting time to each assertion of the Stop signal. The digital values can be analyzed to select the true duration of the event. Other features and embodiments are also provided.

Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.

An analog-based architecture is used to produce tap spacings in an n-tap fractionally-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve fractionally spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the fractionally spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.