A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. The second charge pump unit pumps the first pumped voltage to output a second pumped voltage according to the first clock signal, a fourth clock signal and the third clock signal. The first clock signal and the third clock signal are non-overlapping clock signals. A falling edge of the second clock signal leads a rising edge of the first clock signal. A falling edge of the fourth clock signal leads a rising edge of the third clock signal.

A delay element including a first set of field effect transistors (FETs) with gates configured to receive a first control voltage; a second set of FETs coupled in series with the first set of FETs between a first voltage rail and a first node, respectively, the second set of FETs include gates configured to receive a set of complementary select signals, respectively; a third set of FETs including gates configured to receive a set of non-complementary select signals, respectively; a fourth set of FETs coupled in series with the third set of FETs between a second node and a second voltage rail, respectively, the fourth set of FETs including gates configured to receive a second control voltage; and an inverter coupled between the first node and the second node, the inverter including an input configured to receive an input signal and an output configured to produce an output signal.

A line driver for signal equalization is described. The line driver may comprise an equalization driver and a gating circuit. The gating circuit may be configured to gate the equalization driver between a first transition and a second transition, such as between a rising edge and a falling edge. The gating circuit may comprise one or more delay elements, such as one or more inverters, configured to generate the second transition in response to receiving the first transition, where the second transition is delayed with respect to the first transition. Such line driver may be used to signals having high data rates to transmission lines, such as cables or metal connection on printed circuit boards.

A CMOS all-digital pulse-mixing device includes a plurality of homogeneous logic elements serially connected to form a basic element sequence, an odd-positioned element parallel connection set and an even-positioned element parallel connection set. The basic element sequence includes odd combination positions and even combination positions. The odd-positioned element parallel connection set serially connects with one of the odd combination positions and the even-positioned element parallel connection set serially connects with one of the even combination positions. The odd-positioned element parallel connection set and the even-positioned element parallel connection set are provided to stretch or shrink a pulse mixture, which is distinguished from a conventional full-customized pulse-mixing device.

A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal.

In one example, a device may include a first push-pull driver with a first impedance and a push-pull driver unit with a second push-pull driver having a second impedance. The push-pull driver unit may be in parallel with the first push-pull driver. The device may further include a pulse generating unit to activate the push-pull driver unit for a delay time following an edge transition in an input signal. In one example, the device may have an output impedance that is less than the first impedance when the push-pull driver unit is activated.

A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.

A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

A delay line structure and a delay jitter correction method thereof are provided. The delay line structure comprises N delay units and N selectors. An output end of the N-1th delay unit is connected to a first input end of the N-1th selector and an input end of the Nth delay unit respectively, the N-1th selector inputs the N-1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N-1th selector, and the Nth selector inputs the Nth selection signal. The time delay units and the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first time delay units are connected with input signals and the output ends of the first selectors are connected with output signals.

A semiconductor apparatus may include logic circuits and a control logic. The control logic may be configured to monitor characteristics of the logic circuits to allow the semiconductor apparatus to perform at different operating speeds.