The embodiments of the present disclosure relate to a device for temperature detection, including a delay unit including an odd number of inverters coupled end to end, a switching transistor having a control electrode coupled to an output end of the delay unit, a first electrode coupled to an operating voltage node of the device, and a second electrode coupled to an input end of the delay unit, a first capacitor having a first end coupled to the input end of the delay unit, and a second end coupled to the first electrode of the switching transistor or a ground node of the device, and a temperature sensitive transistor having a control electrode coupled to a bias voltage end of the device, a first electrode coupled to the input end of the delay unit, and a second electrode coupled to the ground node of the device.

A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.

A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media.

Apparatus and methods are described for voltage dependent delay. An example apparatus includes an oscillator including a delay circuit that is configured to provide an oscillating output signal has a delay based on a delay of the delay circuit. The delay of the delay circuit is based on a voltage it receives. For example, the delay of the delay circuit increases for an increasing received voltage and decreases for a decreasing received voltage. As a result, the oscillating output signal provided by the oscillator is based on the received voltage. For example, a frequency of the oscillating output signal decreases for increasing received voltage and increases for decreasing received voltage. Described in another way, the frequency of the oscillating output signal is relatively low for relatively high received voltage and relatively high for relatively low received voltage.

A semiconductor apparatus may include logic circuits and a control logic. The control logic may be configured to monitor characteristics of the logic circuits to allow the semiconductor apparatus to perform at different operating speeds.

The present disclosure provides a power clamp device. The power clamp device includes a delay element, a first transistor, a second transistor, and a gate control circuit. The delay element has an input terminal and an output terminal. The first transistor has a gate electrically connected to the output terminal of the delay element. The second transistor has a source electrically connected to a drain of the first transistor. The gate control circuit has a first terminal electrically connected to the input terminal of the delay element, a second terminal electrically connected to the output terminal of the delay element, and a third terminal electrically connected to a gate of the second transistor.

A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.

A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

A noise detection circuit includes a first delay circuit which has a propagation delay of a first delay time when a signal propagates therethrough and a second delay circuit which has a propagation delay of a second delay time when the signal propagates therethrough, and outputs, based on a sum of the first delay time and the second delay time, a detection result indicating the magnitude of noise on power supply voltage applied to the first delay circuit and the second delay circuit. A control unit controls, based on the detection result, a frequency of a clock signal supplied to a circuit unit to which the power supply voltage is applied and the second delay time in such a manner as to exhibit an opposite behavior to a change in the first delay time induced by temperature.

A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.