An information processing device has a digital-to-pulse converter which outputs a pulse signal including a pulse having a pulse length in accordance with a digital input signal, and a selective oscillator which performs an oscillation operation while the pulse of the pulse signal is output and holds an oscillation operation state at a point of time where the output of the pulse is stopped.

The present utility model relates to an ultra-low voltage two-stage ring voltage-controlled oscillator applied to a chip circuit. The oscillator includes two-stage delay units. The oscillator includes two delay units that are connected end-to-end, and adjusts a working frequency by adjusting delay time of the delay unit. The delay unit includes PMOS transistors M1, M2, M3, and M4, NMOS transistors M5, M6, M7, and M8, and a load capacitor C.sub.L. The two-stage ring voltage-controlled oscillator of the present utility model uses a substrate feed forward bias structure, reduces a threshold voltage of a transistor, reduces a supply voltage, reduces power consumption, has a large tuning range, and is particularly suitable for a system that works at a low supply voltage.

A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first MOS transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second MOS transistor.

A semiconductor apparatus may include logic circuits and a control logic. The control logic may be configured to monitor characteristics of the logic circuits to allow the semiconductor apparatus to perform at different operating speeds.

An anti-floating circuit including a first pull-high circuit, a first pull-low circuit and a first control circuit is provided. The first pull-high circuit includes a first P-type transistor and a second P-type transistor and is coupled to a first power terminal. The first pull-low circuit includes a first N-type transistor and a second N-type transistor and is coupled to a second power terminal. A first path is between the first P-type transistor and the first N-type transistor. A second path is between the second P-type transistor and the second N-type transistor. A third path is between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit turns off the first and second paths and turns on the third path.

An analog-based architecture is used to produce tap spacings in an n-tap fractionally-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve fractionally spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the fractionally spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

A ring oscillator includes first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink current, wherein the first to fourth current-controlled delay circuits are arranged symmetrically to each other about a square.

In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.