A semiconductor apparatus includes a transmission device and a receiving device. The transmission device generates an output signal from a transmission signal in synchronization with a clock signal. The receiving device generates a reception signal from the output signal in synchronization with the clock signal and a delayed clock signal generated by delaying the clock signal by a preset time, based on an operating speed of the semiconductor apparatus.

A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.

In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.

The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals.

In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

Devices and methods for error checking transmissions include using error checking circuitry configured to receive a clock and reset. The error checking circuitry includes an input counter that is configured to receive the clock and to count out multiple input clocks from the received clock. The error checking circuitry also includes a delay model that is configured to receive the clock and to output a delayed clock. Also, the error checking circuitry includes an output counter that is configured to receive the delayed clock and to count out multiple output clocks from the received delayed clock. Furthermore, the error checking circuitry includes multiple error calculation circuits arranged in parallel that each are configured to: receive data based on a respective input clock, generate an error indicator based on the received data with the error indicator indicating whether an error exists in the received data, and output the error indicator based at least in part on a respective output clock.

Superconducting circuits and methods for latching data are described. An example superconducting circuit includes an edge detect circuit configured to receive a logical clock signal and generate a return-to-zero clock signal. The superconducting circuit further includes a first latch configured to receive the logical clock signal and an input data signal, where the first latch is further configured to selectively delay the input data signal to generate a delayed data signal. The superconducting circuit further includes a second latch configured to receive the return-to-zero clock signal and the delayed data signal, where the second latch is further configured to capture a logical high value corresponding to the input data signal in response to a rising edge of the return-to-zero clock signal and capture a low logical value corresponding to the input data signal in response to a falling edge of the return-to-zero clock signal.

A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.

A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.

Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.