An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.

A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.

According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to determine whether at least one of a plurality of delay step sizes is less than at least one of a high pulse width and a low pulse width of a first clock signal and to select one of the delay step sizes and a delay line to delay the first clock signal to produce as second clock signal by a first delay amount that is changed based at least on the one of the delay step sizes.

According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to determine whether at least one of a plurality of delay step sizes is less than at least one of a high pulse width and a low pulse width of a first clock signal and to select one of the delay step sizes and a delay line to delay the first clock signal to produce as second clock signal by a first delay amount that is changed based at least on the one of the delay step sizes.

A switch including multiple current branches and slope circuitry. The slope circuitry activates or deactivates the current branches one at a time according to a corresponding one of multiple slope functions in response to a transition of the input signal. Each current branch develops a current so that the output node follows a predetermined voltage-current function. Each slope function is other than a step function and may be linear or non-linear. A slope function may be configured as a current-starved inverter charging or discharging a capacitor with a fixed current. Delay circuitry may be included to delay the inputs or the outputs of the slope circuitry configured as multiple slope control circuits. The slope control circuits may be daisy-chained from first to last to effectuate the delay. Each current branch may include an electronic switch and may further include a resistor to determine the current level.

A switch including multiple current branches and slope circuitry. The slope circuitry activates or deactivates the current branches one at a time according to a corresponding one of multiple slope functions in response to a transition of the input signal. Each current branch develops a current so that the output node follows a predetermined voltage-current function. Each slope function is other than a step function and may be linear or non-linear. A slope function may be configured as a current-starved inverter charging or discharging a capacitor with a fixed current. Delay circuitry may be included to delay the inputs or the outputs of the slope circuitry configured as multiple slope control circuits. The slope control circuits may be daisy-chained from first to last to effectuate the delay. Each current branch may include an electronic switch and may further include a resistor to determine the current level.

An assembly includes a signal input, a signal output, a pull-up stack coupled to the signal input and to the signal output, a pull-down stack coupled to the signal input and to the signal output, and a hysteresis assembly coupled to the pull-up stack and to the pull-down stack. The pull-up stack comprises a pair of metal oxide semiconductor field-effect transistors (transistors) coupled in series, each transistor of the pair of transistors comprising a gate coupled to the signal input. The pull-down stack comprises a plurality of transistors coupled in series, the plurality of transistors comprising: a first transistor comprising a gate coupled to the signal input, a second transistor comprising a gate coupled to the signal input, and a third transistor. The hysteresis assembly comprises a pair of transistors, each transistor of the pair of transistors of the hysteresis assembly having a gate coupled to the signal output.

An assembly includes a signal input, a signal output, a pull-up stack coupled to the signal input and to the signal output, a pull-down stack coupled to the signal input and to the signal output, and a hysteresis assembly coupled to the pull-up stack and to the pull-down stack. The pull-up stack comprises a pair of metal oxide semiconductor field-effect transistors (transistors) coupled in series, each transistor of the pair of transistors comprising a gate coupled to the signal input. The pull-down stack comprises a plurality of transistors coupled in series, the plurality of transistors comprising: a first transistor comprising a gate coupled to the signal input, a second transistor comprising a gate coupled to the signal input, and a third transistor. The hysteresis assembly comprises a pair of transistors, each transistor of the pair of transistors of the hysteresis assembly having a gate coupled to the signal output.