A pulse signal generation circuit includes a clock frequency division component, a time delay component and a selection component. The clock frequency division component is configured to perform frequency division on a clock signal to generate a clock frequency division signal; the time delay component is configured to generate a time delay signal based on the clock frequency division signal; and the selection component is configured to receive the clock frequency division signal and the time delay signal at the same time, and select the clock frequency division signal and the time delay signal according to a preset condition to generate a pulse signal.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

A sequence signal generator and a sequence signal generation method are provided. In the sequence signal generation method, a waveform output instruction sent by a host computer is received to acquire waveform data. The waveform data includes original square wave sequence data and target square wave sequence data, and the target square wave sequence data includes a preliminary delay parameter and a secondary delay parameter. An original square wave sequence signal is acquired according to the original square wave sequence data. According to the preliminary delay parameter, preliminary delay processing is performed on the original square wave sequence signal to acquire an intermediate square wave sequence signal, and according to the secondary delay parameter, secondary delay processing is performed on the intermediate square wave sequence signal to acquire a target square wave sequence signal.

A timer includes a timing counter configured to generate a timing datum, a clock pulse signal generation circuit configured to generate a clock pulse signal used to operate the timing counter, and an interface circuit configured to receive an access signal, wherein the timing counter is an asynchronous counter, and the clock pulse signal generation circuit generates the clock pulse signal having a first pulse width when there is a possibility that the interface circuit receives the access signal, and generates the clock pulse signal having a second pulse width longer than the first pulse width when there is no possibility that the interface circuit receives the access signal.

A semiconductor device includes a test clock generation circuit, a test data generation circuit, and a control code generation circuit. The test clock generation circuit delays a clock signal based on a delay selection signal in a test mode to generate a test clock signal. The test data generation circuit delays data to generate test data. The control code generation circuit latches the test data based on the delay selection signal and the test clock signal to generate a control code.

A semiconductor device includes a test clock generation circuit, a test data generation circuit, and a control code generation circuit. The test clock generation circuit delays a clock signal based on a delay selection signal in a test mode to generate a test clock signal. The test data generation circuit delays data to generate test data. The control code generation circuit latches the test data based on the delay selection signal and the test clock signal to generate a control code.

A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.