A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.

A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.