Various techniques are provided to correct the duty cycles and convert differential clock signals in synchronized systems. In one example, a method includes receiving an input differential clock signal having a distorted duty cycle. The method also includes adjusting the input differential clock signal to provide an output differential clock signal with a corrected duty cycle. The adjusting is performed in response to signals provided by a differential amplifier and a common mode amplifier of an analog feedback circuit receiving the output differential clock signal. Additional methods and systems are also provided.

Various techniques are provided to correct the duty cycles and convert differential clock signals in synchronized systems. In one example, a method includes receiving an input differential clock signal having a distorted duty cycle. The method also includes adjusting the input differential clock signal to provide an output differential clock signal with a corrected duty cycle. The adjusting is performed in response to signals provided by a differential amplifier and a common mode amplifier of an analog feedback circuit receiving the output differential clock signal. Additional methods and systems are also provided.

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

Certain aspects of the present disclosure provide a voltage transient detection circuit. The circuit generally includes a first switch having a first terminal coupled to an input signal source node, and a second switch having a first terminal coupled to the input signal source node. The apparatus includes a first shunt capacitive element coupled to a second terminal of the first switch, a second shunt capacitive element coupled to a second terminal of the second switch, a differential circuit having a first input coupled to the second terminal of the first switch, a second input coupled to the second terminal of the second switch, and an output coupled to an output node of the voltage transient detection circuit. For certain aspects, the apparatus also includes a first current source (selectively) coupled to the first shunt capacitive element and a second current source (selectively) coupled to the second shunt capacitive element.

Certain aspects of the present disclosure provide a voltage transient detection circuit. The circuit generally includes a first switch having a first terminal coupled to an input signal source node, and a second switch having a first terminal coupled to the input signal source node. The apparatus includes a first shunt capacitive element coupled to a second terminal of the first switch, a second shunt capacitive element coupled to a second terminal of the second switch, a differential circuit having a first input coupled to the second terminal of the first switch, a second input coupled to the second terminal of the second switch, and an output coupled to an output node of the voltage transient detection circuit. For certain aspects, the apparatus also includes a first current source (selectively) coupled to the first shunt capacitive element and a second current source (selectively) coupled to the second shunt capacitive element.

Implementation of large temperature-insensitive resistance in CMOS using short-duty-clock cycle is provided herein. Operations of a method can comprise boosting a resistance level of a switched-resistor circuit to a defined resistance level. The boosting can comprise using a short-duty-cycle clock to facilitate the boosting. Also provided is a sensor system that can comprise a short-duty-cycle clock and a switched-resistor circuit. The short-duty cycle clock boosts a resistance level of the switched-resistor circuit to a defined resistance level.

The invention relates to a time-delay circuit (1) for a digital signal (3), particularly for a clock signal, comprising:

an input (2) for the digital signal (3);
an oscillator (4) for generating an internal clock signal (5);
at least one delay channel (6) adding a certain delay to the digital input signal (3) based on the internal clock signal (5); and
an output (7) for a delayed digital signal (8).