Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

A data slicer for converting an envelope signal of an amplitude-modulated wave into a binary signal, comprises: an average level generation circuit configured to generate an average level of the envelope signal by averaging the envelope signal per time; a fixed voltage value generation circuit configured to generate a fixed voltage value; a reference level generation circuit configured to generate a reference level in accordance with the fixed voltage value and the average level of the envelope signal; and a comparison circuit configured to compare a signal level of the envelope signal with the reference level to output a result of the comparison as the binary signal.

A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.

Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.

A dynamic vision sensor includes a pixel unit, including a plurality of pixels outputting an activation signal in response to dynamic input, a first reading unit outputting a first signal, based on the activation signal, a second reading unit outputting a second signal, based on the activation signal, an event counter counting the number of events generated, based on the activation signal, and generating and outputting a selection signal, based on the number of events, and a selecting unit outputting one of the first signal and the second signal, based on the selection signal.

Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE.sub.1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE.sub.2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.