An operator control element in a motor vehicle generates an activation signal as a function of the activation of the operating element, and a control unit receives the activation signal and measures a signal length of the activation signal, and signals the activation if the signal length becomes greater than a predetermined debounce time. Despite possible incorrect triggering of the activation signal owing to voltage fluctuations, the debounce time is to be short. The control unit determines for this purpose an operating parameter, and on the basis of the operating parameter it is detected that a supply voltage, made available at the control unit, satisfies a predetermined instability criterion, and when the instability criterion is satisfied the control unit delays the measurement of the signal length for a predetermined blocking time.

An operator control element in a motor vehicle generates an activation signal as a function of the activation of the operating element, and a control unit receives the activation signal and measures a signal length of the activation signal, and signals the activation if the signal length becomes greater than a predetermined debounce time. Despite possible incorrect triggering of the activation signal owing to voltage fluctuations, the debounce time is to be short. The control unit determines for this purpose an operating parameter, and on the basis of the operating parameter it is detected that a supply voltage, made available at the control unit, satisfies a predetermined instability criterion, and when the instability criterion is satisfied the control unit delays the measurement of the signal length for a predetermined blocking time.

Disclosed herein are various implementations of input-controlled multiple threshold debounce circuits or algorithms. In one embodiment, an input-controlled multiple threshold debounce system is configured to receive an input signal and to control an output. An analysis subsystem may determine when an input signal exceeds an assertion threshold and may assess at least one additional characteristic of the input signal. Supervisory logic in communication with the analysis subsystem may select a variable delay based on the at least one additional characteristic of the input signal. A delay subsystem controlled by the supervisory logic may assert a first signal after the input signal remains above the assertion threshold for longer than the variable delay. Finally, a system output may be configured to receive the first signal and may be configured to assert the debounce system output based on the first signal.

Disclosed herein are various implementations of input-controlled multiple threshold debounce circuits or algorithms. In one embodiment, an input-controlled multiple threshold debounce system is configured to receive an input signal and to control an output. An analysis subsystem may determine when an input signal exceeds an assertion threshold and may assess at least one additional characteristic of the input signal. Supervisory logic in communication with the analysis subsystem may select a variable delay based on the at least one additional characteristic of the input signal. A delay subsystem controlled by the supervisory logic may assert a first signal after the input signal remains above the assertion threshold for longer than the variable delay. Finally, a system output may be configured to receive the first signal and may be configured to assert the debounce system output based on the first signal.

An expansion control circuit includes a delay circuit coupled to a first expansion module and a switching circuit coupled to a second expansion module. The switching circuit includes a buffer and a switching module. The buffer is coupled to the first expansion module. The first expansion module outputs a first control signal upon being switched on and outputs a second control signal after a working time. The delay circuit outputs a disconnecting signal upon being switched on. The buffer is switched off upon receiving the disconnect signal. The delay circuit further outputs a connecting signal after a delay time after outputting the disconnecting signal. The buffer is switched on upon receiving the connect signal. The buffer further outputs the second control signal to the switching module upon being switched on. The switching module controls the second expansion module to be switched on v receiving the second control signal.

An expansion control circuit includes a delay circuit coupled to a first expansion module and a switching circuit coupled to a second expansion module. The switching circuit includes a buffer and a switching module. The buffer is coupled to the first expansion module. The first expansion module outputs a first control signal upon being switched on and outputs a second control signal after a working time. The delay circuit outputs a disconnecting signal upon being switched on. The buffer is switched off upon receiving the disconnect signal. The delay circuit further outputs a connecting signal after a delay time after outputting the disconnecting signal. The buffer is switched on upon receiving the connect signal. The buffer further outputs the second control signal to the switching module upon being switched on. The switching module controls the second expansion module to be switched on v receiving the second control signal.

A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.

A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.

A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.

A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.