A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.

An integrated circuit having: a signal output circuit configured to output a first digital signal of a first logic level or of a second logic level in response to an analog signal; a first buffer circuit configured to raise and lower a voltage at a terminal of the integrated circuit in response to the first digital signal of a first logic level and a second logic level, respectively; a first digital delay circuit configured to receive a clock signal, and to delay the first digital signal, to output a resultant signal as a first delay signal, based on the received clock signal; and a second buffer circuit configured to raise the voltage at the terminal in response to the first delay signal of the first logic level, and lower the voltage at the terminal in response to the first delay signal of the second logic level.

An integrated circuit having: a signal output circuit configured to output a first digital signal of a first logic level or of a second logic level in response to an analog signal; a first buffer circuit configured to raise and lower a voltage at a terminal of the integrated circuit in response to the first digital signal of a first logic level and a second logic level, respectively; a first digital delay circuit configured to receive a clock signal, and to delay the first digital signal, to output a resultant signal as a first delay signal, based on the received clock signal; and a second buffer circuit configured to raise the voltage at the terminal in response to the first delay signal of the first logic level, and lower the voltage at the terminal in response to the first delay signal of the second logic level.

A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. The second charge pump unit pumps the first pumped voltage to output a second pumped voltage according to the first clock signal, a fourth clock signal and the third clock signal. The first clock signal and the third clock signal are non-overlapping clock signals. A falling edge of the second clock signal leads a rising edge of the first clock signal. A falling edge of the fourth clock signal leads a rising edge of the third clock signal.

The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V−), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V−), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.

The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V−), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V−), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.

A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.

A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.