In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

A phase controller includes a plurality of pulse width modulation (PWM) circuits, a plurality of switching devices, a computing unit, and a latency generator. The plurality of PWM circuits output pulse signals. The plurality of switching devices are coupled to the respective plurality of PWM circuits, and switch on and off based on the pulse signals. The computing unit calculates the pulse signals to be output from the plurality of PWM circuits, based on outputs of the plurality of switching devices. The latency generator generates latency in any of the pulse signals so that edge positions of the pulse signals output from the plurality of PWM circuits do not collide with each other, wherein the pulse signals change values at the edge positions.

Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.

Digital-to-analog converter (master DAC) circuitry is disclosed that is programmable to set a controlled slew rate for pulses that are otherwise defined as having sharp amplitude transitions. For example, when producing a biphasic pulse, the constant amplitude and duration of first and second pulses phases can be defined and provided to the DAC in traditional fashion. Slew rate control signals control a slew rate DAC within the master DAC, which prescribes a slew rate that will appear at sharp transitions of the defined biphasic pulses, i.e., at the beginning of the first phase, at the transition from the first to the second phase, and at the end of the second phase. The slew rate can vary with the duration or frequency of the pulses, with lower slew rates used with longer durations and/or lower frequencies, and with higher slew rates used with shorter durations and/or higher frequencies.

In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Current generation circuitry for an Implantable Pulse Generator (IPG) is disclosed. The IPG comprises a plurality of PDACs and NDACs for souring currents to electrode nodes. The PDACs and NDACs can be configured as pairs to each provide stimulation in independent timing channels, or the PDACs can be combined and the NDACs can be combined to provide stimulation in a single timing channel. Further, the PDAC or NDAC can provide a plurality of source branch currents each of the same amplitude to the electrodes via a switch matrix, and pulse definition circuitry can be configured to always connect each of the source branch currents to one of the first one or more electrode nodes via the switch matrix.

A phase controller includes a plurality of pulse width modulation (PWM) circuits, a plurality of switching devices, a computing unit, and a latency generator. The plurality of PWM circuits output pulse signals. The plurality of switching devices are coupled to the respective plurality of PWM circuits, and switch on and off based on the pulse signals. The computing unit calculates the pulse signals to be output from the plurality of PWM circuits, based on outputs of the plurality of switching devices. The latency generator generates latency in any of the pulse signals so that edge positions of the pulse signals output from the plurality of PWM circuits do not collide with each other, wherein the pulse signals change values at the edge positions.

Methods and apparatus for generating multiple phase-shifted clock signals from a base clock signal using programmable delays at the leaf level in a clock distribution network are described. One example method for generating and distributing multiple phase-shifted clock signals in a programmable integrated circuit (IC) generally includes generating a base clock signal, routing the base clock signal through a clock distribution network in the programmable IC to a leaf node, and applying one or more programmable delays to the base clock signal received from the leaf node to generate the multiple phase-shifted clock signals.