A semiconductor device includes: a first semiconductor die and a second semiconductor die connected on the first semiconductor die, in which the first semiconductor die includes buffers in a second-stage configuration to an Nth-stage configuration (N being an integer of 3 or more) in a clock tree structure, and the second semiconductor die includes a logic circuit electrically connected to the buffer in the Nth-stage configuration.

A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured to disable the control clock signal in response to the completion signal indicating a completion of required conversion cycles in a conversion phase.

A two-stage 4-phase clock buffer having a cascade of a first stage and a second stage, wherein: the first stage includes four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock; and, the second stage includes four NMOS transistors configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOS transistors configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.

A processing chip includes a first sub-circuit, an asynchronous clock interface circuit, and a second sub-circuit. The asynchronous clock interface circuit includes a first beat conversion circuit, a first trigger circuit, and a second beat conversion circuit. A first signal end of the first sub-circuit is coupled to a trigger input end of the first trigger circuit. A trigger output end of the first trigger circuit is separately coupled to an input end of the first beat conversion circuit and an input end of the second beat conversion circuit. An output end of the first beat conversion circuit is coupled to a third signal end of the first sub-circuit. An output end of the second beat conversion circuit is coupled to a second signal end of the second sub-circuit.