A multi-phase signal control circuit includes: a comparator, configured to compare a triangular wave signal with a feedback control signal to output a first pulse width modulation signal, where the feedback control signal is a signal fed back by the power stage circuit; a phase switch circuit, configured to receive a phase switch signal and the first pulse width modulation signal to generate a first phase signal and a second phase signal, where the first phase signal and the second phase signal are used to control the power stage circuit to generate an output voltage signal.

The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

A differential amplifier circuit generates a first current and a second current having a current difference obtained by amplifying a voltage difference between an input voltage and a reference voltage. An output stage supplies current proportional to the first current to an output node. A current conversion circuit discharges current proportional to the second current from the output node. After connecting the output node to a ground node in response to a reset signal, a latch circuit disconnects the output node from the ground node after reset cancellation. Thereafter, when voltage at the output node rises from the ground voltage in a case where a level relationship between the input voltage and the reference voltage is reversed from a reset cancellation time point, the latch circuit fixes the voltage at the output node to a power supply voltage by a positive feedback latch operation.

A clock synchronization signal generator generates a dead time in which gates of both of two switching elements included in a switching circuit are in an off state, and generates the dead time for controlling a plurality of pulses having different widths to pulses having a constant width, which is output by the switching circuit.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ( )}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ( )}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ( )}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ( )}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ( )}(n−1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ( )}(n−1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ( )}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ( )}(n−1) odd stages or the 2{circumflex over ( )}(n−1) even stages to collectively generate a 2{circumflex over ( )}(n−1) phase signal in a second mode.

Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes an electronic circuit, a first set of SCRC switches, and a second set of SCRC switches. The electronic circuit includes first circuitry and second circuitry. The first set of SCRC switches are at one or more SCRC regions of an integrated circuit device including the electronic circuit. The first set of SCRC switches are configured to provide power to the first circuitry. At least one second SCRC switch of the second set of SCRC switches is positioned between one of the first set of SCRC switches and another of the first set of SCRC switches. The second set of SCRC switches is configured to provide power to the second circuitry.

A multi-phase signal control circuit includes: a comparator, configured to compare a triangular wave signal with a feedback control signal to output a first pulse width modulation signal, where the feedback control signal is a signal fed back by the power stage circuit; a phase switch circuit, configured to receive a phase switch signal and the first pulse width modulation signal to generate a first phase signal and a second phase signal, where the first phase signal and the second phase signal are used to control the power stage circuit to generate an output voltage signal.

Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes an electronic circuit, a first set of SCRC switches, and a second set of SCRC switches. The electronic circuit includes first circuitry and second circuitry. The first set of SCRC switches are at one or more SCRC regions of an integrated circuit device including the electronic circuit. The first set of SCRC switches are configured to provide power to the first circuitry. At least one second SCRC switch of the second set of SCRC switches is positioned between one of the first set of SCRC switches and another of the first set of SCRC switches. The second set of SCRC switches is configured to provide power to the second circuitry.

A control circuit for an inverter. The control circuit includes a first pulse width modulation (PWM) module configured to produce first and second complimentary PWM signals, and a second PWM module configured to produce a third and fourth complimentary PWM signals. PWM switching logic is coupled to the first and second PWM modules and is adapted to be coupled to a switch network. The switch network includes first, second, third, and fourth switches coupled in series between a first voltage terminal and a second voltage terminal. The PWM switching logic is configured to produce control signals for each of the first, second, third, and fourth switches in response to the first and second complimentary PWM signals and to the third and fourth complimentary PWM signals.

A sensor system includes a pixel array, a DC/DC converter, and a photodiode stack. The pixel array is configured to operate in an image capturing mode or an energy harvesting mode. The DC/DC converter is configured to convert energy captured by the pixel array while in energy harvesting mode. The photodiode stack is located adjacent to the pixel array and configured to provide power to the DC/DC converter.