A switch-node rising edge detection circuit is provided for a switched-mode DC/DC boost converter. A high-side gate-driver couples a gate of the high-side NMOS power transistor to either a first terminal of a bootstrap capacitor or the switch-node. The detection circuit includes an AND gate that receives an activation signal on a first input and provides a switching signal to the high-side gate-driver. A PMOS transistor is coupled in series with an inverter between the first terminal of the bootstrap capacitor and a second input of the AND gate. The inverter receives supply voltages from the first terminal of the bootstrap capacitor and the switch-node. The gate of the PMOS transistor receives the activation signal. An NMOS transistor is coupled between an output voltage and a node between the PMOS transistor and the inverter. A gate of the NMOS transistor is coupled to the bootstrap capacitor's first terminal.

A signal generation circuit generates first and second non-overlapping digital signals from an input pulse signal. A first digital circuit includes: a first logical OR gate receiving the second digital signal and the input pulse signal to generate a third digital signal; and a second logical OR gate receiving the input pulse signal and a delayed version of the third digital signal to generate the first digital signal. A second digital circuit includes: a first logical AND gate receiving the first digital signal and the input pulse signal to generate a fourth digital signal; and a second logical AND gate receiving the input pulse signal and the fourth digital signal to generate the second digital signal.

A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

An electronic device includes clock generation circuitry. The clock generation circuitry includes a first flip flop receiving as input a device clock and being triggered by an input clock and a second flip flop receiving, as input, output from the first flip flop and being triggered by the input clock. A first inverter receives output from the first flip flop as input and a second inverter receives output from the second flip flop as input. A first AND gate receives, as input, output from the second flip flop and the first inverter, and generates a first clock as output. A second AND gate receives, as input, output from the first flip flop and the second inverter, and generates a second clock as output.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.

A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.

Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.