Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. Phase change element includes first terminal and second terminal. First switch includes first terminal and second terminal. Second switch includes first terminal, second terminal, and control terminal. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch. Second switch is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch. Second pulse signal flows through second switch to control state of phase change element to determine weight of artificial neuromorphic circuit.

Disclosed herein is a voltage comparator including a first capacitor, a first inverter and a first switch connected in series and provided between both ends of the first capacitor, a second inverter connected in parallel with the first inverter, a second switch provided between an input and an output of the first inverter, a third switch provided between an input and an output of the second inverter, a second capacitor provided between the output of the first inverter and the input of the second inverter, a third capacitor provided between the output of the second inverter and the input of the first inverter, and a fourth switch provided in one of a position between an upper electrode of the first capacitor and a power supply line and a position between a lower electrode of the first capacitor and a ground line.

The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.

A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

A system for processing a signal in a signal chain having decentralized embedded power management of components of the signal chain includes an input circuit to generate a measurement signal responsive to a stimulus, where the measurement signal is indicative of a characteristic of the stimulus. The system additionally includes a signal converter circuit coupled to the input circuit to convert the measurement signal to a digital signal according to a timing condition for capturing a sample of the measurement signal. The signal converter includes a control circuit to provide electrical power to the input circuit based on the timing condition and a sampling circuit to capture the sample of the measurement signal responsive to an indicator signal generated by the sensor circuit.

A low power comparator circuit is provided. The circuit includes a comparator core including a first stage. The first stage has an output configured to provide a digital value. A capacitor includes a first terminal coupled at an input of the first stage and a second terminal selectively coupled to a first input and a second input of the comparator core. A voltage generator is coupled to the first stage. The voltage generator is configured and arranged to generate a first voltage based on a predetermined input current and to limit a maximum current of the first stage based on the predetermined input current.

One example discloses a differential-signal-detection circuit, including: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal; a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal; wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

The present description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A′, 110B′, 106, 108) in series, wherein: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A′, 110B′) gate is controllable and is associated with another gate; each controllable gate (110A′, 110B′) comprises a control input (116) coupled with the output (102) of said associated gate, and prevents switching of its output (102) to a high state if its control input (116) is in the high state, and to a low state otherwise; and the control input (116) of each controllable gate (110A′, 110B′) receives the output (102) of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not.

A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.

A comparator receives a target voltage and a reference voltage at its inverting and non-inverting input terminals, and outputs a signal corresponding to the level relationship between those voltages A node provided on the output side of the comparator is fed with a signal equivalent to the output signal of the comparator. Between the node and the non-inverting input terminal of the comparator, a capacitor is inserted.