A bootstrap circuit supporting fast charging and discharging and a chip. A voltage measurement module (12) and a switch module (11) are arranged, and the voltage measurement module (12) controls an operating state of the switch module (11); during charging, under a specific condition, the switch module (11) is enabled to be in an on state so as to achieve fast charging of a voltage output end; and during discharging, the purpose of fast discharging is achieved by means of a second field effect transistor (MP5) arranged in the bootstrap circuit.

A level shifter and an electronic device are provided. The electronic device includes a digital circuit and a level shifter. The level shifter converts a first and a second input signals to an output signal. The level shifter includes a cross-coupled circuit, a protection circuit, and a pull-down module. The cross-coupled circuit includes a first and a second pull-up transistors. The protection circuit includes a first and a second protection transistors. The pull-down module includes a first and a second pull-down circuits and a first and a second switching circuits. The first and the second pull-up transistors, the first and the second protection transistors, and the first and the second pull-down circuits are selectively switched on in response to the first and the second input signals. The digital circuit receives the output signal from the level shifter.

In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.

A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

A method and device for adjusting the switching speed of a MOSFET are disclosed. The MOSFET is connected to drive switch, the collector of the drive switch is connected to the grid of the MOSFET through the grid resistor, the emitter of the drive switch is grounded through the emitter resistor, and the collector of the drive switch is also connected to the source resistor through the collector resistor, the other end of the source resistor is connected to the source of the MOSFET; the drain of the MOSFET is connected to the current source. The method comprises: obtaining the adjustment target of the switching speed for the MOSFET, determining the first resistance value of the emitter resistor and/or the second resistance value of the collector resistor based on said adjustment target, controlling the operation of the MOSFET according to the adjusted resistance value.

An electronic solid-state switch assembly includes a base plate and a heat exchanger; an electrically insulating layer and a direct bonded substrate affixed to the base plate; a first terminal and a second terminal; a plurality of power transistors; a plurality of gate drivers; a communication interface, a current sensor, and a snubber circuit; and a controller. The plurality of gate drivers are operatively coupled to the plurality of power transistors. The plurality of power transistors are arranged in parallel on the direct bonded substrate between the first terminal and the second terminal. The plurality of power transistors are electrically connected to the first terminal and to the second terminal. The controller is in communication with the plurality of gate drivers, the current sensor, and the communication interface. The controller is configured to control, via the plurality of gate drivers, the plurality of power transistors.

Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack. In addition, multiple FET stacks are implemented in parallel in at least some switch branches to improve settling time for the branch.

This disclosure relates to a system that includes a boost circuit comprising a boost capacitor. The boost circuit is configured to provide a boost voltage at a first terminal of the boost capacitor by increasing the boost voltage at the first terminal to exceed a target voltage for a given charge cycle. A boost switch is configured to supply the boost voltage from the first terminal to a charge node for turning on a transistor, which is coupled to the charge node, based on a boost signal during the given charge cycle. A pull-down circuit is configured to control discharge of the charge node to a clamp voltage that is sufficient to turn off the transistor for the given charge cycle and to facilitate charging of the charge node in a next charge cycle.

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

A circuit includes an electronic component package that comprises a first lead, a second lead, and a third lead; and a III-N transistor encased in the electronic component package, the III-N transistor including a drain, a gate, and a source, where the source is coupled to the first lead, the gate is coupled to the second lead, and the drain is coupled to the third lead. The circuit includes a high voltage node and a resistor, the resistor having a first terminal coupled to the high voltage node and a second terminal coupled to the third lead. The circuit further includes a ferrite bead connected in parallel to the resistor and coupled between the third lead and the high voltage node. When switching, the deleterious effects of a parasitic inductance of the circuit's power loop are mitigated by the ferrite bead and the resistor.