Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

A circuit for quenching an avalanche photodiode (APD) detector is disclosed herein. The circuit may comprise a discrete transistor configured to draw a quench current so as to enable a drop in a reverse bias voltage applied to the APD detector, and an integrated circuit connected to the discrete transistor, the integrated circuit including a plurality of circuit elements for controlling the reverse bias voltage.

A circuit for quenching an avalanche photodiode (APD) detector is disclosed herein. The circuit may comprise a discrete transistor configured to draw a quench current so as to enable a drop in a reverse bias voltage applied to the APD detector, and an integrated circuit connected to the discrete transistor, the integrated circuit including a plurality of circuit elements for controlling the reverse bias voltage.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

A FET driving circuit includes: two inputs for inputting a DC voltage; two outputs respectively connected to gate and source electrodes of a FET; a switch; a resonant capacitance connected between both ends of the switch; and an LC resonance circuit connected between the inputs and both ends of the switch. When the two inputs are shorted, frequency characteristics of an impedance of the LC resonance circuit include, in order from a low to a high-frequency side, first to fourth resonant frequencies. The first resonant frequency is higher than a switching frequency of the switch, the second resonant frequency is around double the switching frequency, the fourth resonant frequency is around four times the switching frequency, and the impedance has local maxima at the first resonant frequency and the third resonant frequency and local minima at the second resonant frequency and the fourth resonant frequency.

An apparatus that includes a first device connected to an inductor. The first device includes a first silicon carbide (SiC) junction gate field-effect transistor (JFET), a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET, and a first silicon (Si) transistor connected to transmit current to a source of the first SiC JFET. An inductor input terminal is connected to the drain of the first SiC JFET.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

A circuit and a corresponding method for driving one or more electric loads are described, comprising: a generator (110) of an electric current waveform, and a passive filter (150) connected in input to the generator (110) and in output to each electric load (105) to be driven, wherein the passive filter (150) is tuned for generating an electric current waveform resulting from a conditioning of one or more harmonics of the electric current waveform in input.

A circuit and a corresponding method for driving one or more electric loads are described, comprising: a generator (110) of an electric current waveform, and a passive filter (150) connected in input to the generator (110) and in output to each electric load (105) to be driven, wherein the passive filter (150) is tuned for generating an electric current waveform resulting from a conditioning of one or more harmonics of the electric current waveform in input.

To realize a reduction in the number of parts in a system including a driver IC (semiconductor device). A high potential side power supply voltage is applied to a power supply application area. A high side area is formed with a circuit which includes a driver driving a high side transistor and is operated at a boot power supply voltage with a floating voltage as a reference. A low side area is formed with a circuit operated at a power supply voltage with a low potential side power supply voltage as a reference. A first termination area is disposed in a ring form so as to surround the power supply application area. A second termination area is disposed in a ring form so as to surround the high side area.