A power semiconductor circuit is provided for clamping the voltage across the circuit when a power semiconductor switch is opened (i.e., turned off). The circuit may include a first surge arrester and a first semiconductor switch coupled in parallel with the power semiconductor switch. The first semiconductor switch is coupled in series with the first surge arrester. A second surge arrester may be coupled to the gate of the first semiconductor switch to control current flow through the first semiconductor switch and the first surge arrester.

The invention relates to a method and an actuating arrangement for controlling a MOSFET, in particular wide-bandgap MOSFET. A change of an actuating variable, which actuates the MOSFET as a function of an operating characteristic variable that influences the switching behavior of the MOSFET is stored in a characteristic block. The change counteracts a reference actuating value of the actuating variable. An actual value of the operating characteristic variable is determined during operation of the MOSFET, The actuating variable is changed from the reference actuating value as a function of the actual value commensurate with the change of the actuating variable stored in the characteristic block. The change stored in the characteristic block can include a change in the switch-on or switch-off voltage or gate resistance of the MOSFET as a function of the operating temperature or the operating voltage of the MOSFET.

Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.

An electronic switch includes a turn-off semiconductor switch, a capacitor, a varistor, with the capacitor and the varistor being arranged in a first series circuit which is arranged in parallel with the turn-off semiconductor switch, a switch, and a resistor, with the switch and the resistor being arranged in parallel with the turn-off semiconductor switch and with the first series circuit.

A linear power supply circuit includes: an output stage including a first output transistor and a second output transistor, which are provided between an input terminal to which an input voltage is able to be applied and an output terminal to which an output voltage is able to be applied and are connected in parallel to each other; a driver configured to drive the first output transistor and the second output transistor based on a difference between a voltage based on the output voltage and a reference voltage; a resistor inserted between a gate of the first output transistor and a gate of the second output transistor; a capacitor having one end connected to the input terminal and the other end connected to a connection node between the resistor and the gate of the second output transistor; and a clamp element connected in parallel to the resistor.

A switching device for a supply line for supplying electrical loads with electricity includes a power input, a power output, a controlled switching element, and a regulated resistance. The controlled switching element is disposed electrically between the power input and the power output and is configured to electrically couple the power input to the power output in a controlled manner. The regulated resistance is disposed electrically parallel to the controlled switching element. The regulated resistance is configured to electrically connect the power input to the power output during opening of the controlled switching element and occurring of voltage spikes between the power input and the power output. A voltage supply system, a method, and a manufacturing method are provided.

A method is described. The method comprises determining a first measurement signal (CS1) which depends on a first load current (I1) through a first transistor (Q1) which is connected in series to a load (Z); determining a second measurement signal (CS2) which depends on a second load current (I2) through a second transistor (Q2) which is connected in series to the load (Z); and comparing the first measurement signal (CS1) and the second measurement signal (CS2), in order to detect the presence of an error.

A switch device includes a first node, a switch unit, an adjustment switch, an impedance element, a second node and a detection unit. A first terminal of the switch unit is coupled to the first node. A first terminal and a second terminal of the adjustment switch are respectively coupled to a second terminal of the switch unit and a reference voltage terminal. A first terminal and a second terminal of the impedance element are respectively coupled to the first terminal and the second terminal of the adjustment switch. The detection unit is coupled to the second node, and a control terminal of the switch unit and a control terminal of the adjustment switch. The detection unit detects a node signal at the second node to accordingly control the switch unit and the adjustment switch.

A circuit for detecting failure of a device includes an on-phase detector, an off-phase detector, and protection switch circuitry. The on-phase detector is configured to determine whether a first failure has occurred at the device based on a rate of change of a current at a high-side switching element. The off-phase detector is configured to determine whether a second failure has occurred at the device based on both a current at a low-side switching element and a voltage at a switch node that is electrically coupled to the high-side switching element and the low-side switch. The protection switch circuitry is configured to electrically disconnect the high-side switching element from a supply circuit in response to the on-phase detector determining that the first failure has occurred at the device or in response to the off-phase detector determining that the second failure has occurred at the device.

A protected direct-drive depletion-mode (D-mode) GaN semiconductor half-bridge power module is disclosed. Applications include high power inverter applications, such as 100kW to 200kW electric vehicle traction inverters, and other motor drives. The high-side switch is a normally-on D-mode GaN semiconductor power switch Q1 in series with a normally-off LV Si MOSFET power switch M1 and the low-side switch is a normally on D-mode GaN semiconductor power switch Q2. The gates of both Q1 and Q2 are directly driven. M1 in series with Q1 provides a high-side switch which is a normally-off device for start-up and fail-safe protection. M1 may also be used for current sensing and overcurrent protection. For example, a control circuit determines an operational mode of M1 responsive to a UVLO signal and a voltage sense signal indicative of an overcurrent event. Examples of single phase and three-phase half-bridge modules and driver circuits are described.