An adjustable three output DC voltage supply circuit includes positive and negative DC voltage buses that connect to a DC power source; a first voltage divider connected between the positive and negative DC voltage buses and including a shunt regulator that is connected to the positive DC voltage bus and that provides an intermediate voltage supply; a second voltage divider connected between the positive or the negative DC voltage bus and the intermediate voltage supply and including an output that is connected to a reference input of the shunt regulator; and a short circuit protection component connected in series to a low voltage side of the shunt regulator and configured to limit the current through the shunt regulator in the case of a short circuit to the intermediate voltage supply.

A power supply circuit for providing a positive, intermediate, and negative voltage supply includes positive and negative DC voltage buses that connect to a power source; a first voltage divider that is connected between the positive and the negative DC voltage buses, that includes a first transistor connected to the negative DC voltage bus, and that provides the intermediate voltage supply; a second voltage divider that is connected between the positive and the negative DC voltage buses and that is connected to the first transistor; and a short circuit protection module that includes a second transistor connected between outputs of the first and second voltage dividers and connected to the first transistor and that includes a current limiting element connected to the first transistor and configured to limit power dissipated by the first transistor in the case of a short circuit to the intermediate voltage supply.

An electronic valve apparatus for a high voltage direct current, HVDC, power transmission system. The electronic valve apparatus includes a first device chain including a number of first devices connected in series between an input node and an output node. Each of the first devices has an asymmetric transfer function configured substantially to block current flow through the device in a first direction, and the first devices are connected such that they all block current flow in the same direction. The electronic valve apparatus also includes a second device chain including a number of second devices connected in series between the input node and the output node. Each of the second devices has an asymmetric transfer function configured substantially to block current flow through the device in a first direction, and the second devices are connected such that they all block current flow in the same direction.

A controller comprising a driver interface referenced to a first reference potential, a drive circuit referenced to a second reference potential, and an inductive coupling. The driver interface comprises a first receiver configured to compare a portion of signals having a first polarity on the first terminal of the inductive coupling with a first threshold, and a second receiver configured to compare a portion of signals having a second polarity on the second terminal of the inductive coupling with a third threshold. The drive circuit comprises a first transmitter configured to drive current in a first direction in the second winding to transmit first signals, and a second transmitter configured to drive current in a second direction in the second winding to transmit second signals, the second direction opposite the first direction.

Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET and thereby commutating a first shutoff current through a lower base of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

An input output circuit and an electrostatic discharge (ESD) protection circuit are provided. The ESD protection circuit is adapted to a charged-device model (CDM). The ESD protection circuit includes a bipolar junction transistor (BJT). The BJT has a first end coupled to an input end of an input buffer and an output end of an output buffer. A second end of the BJT is coupled to a first ground rail. A control end of the BJT is coupled to one of a first power rail, a second power rail, the first ground rail and a second ground rail.

This disclosure is directed to circuits and techniques for protecting a power switch when the power switch is turned ON. A driver circuit may detect whether the power switch is in a desaturation mode or an overcurrent state based on a signal at a detection pin, and disable the power switch in response to detecting that the power switch is in the desaturation mode or the overcurrent state. In addition, the driver circuit may detect whether the power switch is trending towards a safe operating area (SOA) limit of the power switch based on a rate of change of the signal, and disable the power switch in response to detecting that the power switch is trending towards the SOA limit.

A controller for a power converter having at least a first switch and a second switch. Each switch is a transistor with a collector terminal, an emitter terminal, and a base terminal. The controller is connectable to the base terminals of the first and second switches to provide a base current to the base terminals of the first and second switches, and connectable to the emitter terminals of the first and second switches to provide a short-circuit between the base and emitter terminals of the first and second switches. The controller also comprises a timing circuit for controlling the provision of the base current and the short-circuit in a sequence. An associated method is also provided.

An amplifier overload power limit circuit, system, and a method thereof comprising a monitoring of a current gain of a BJT based on a current detector and limiting power to the BJT based on the monitored current gain to prevent the BJT from driven into a saturation mode and the amplifier overdrive.

An input output circuit and an electrostatic discharge (ESD) protection circuit are provided. The ESD protection circuit is adapted to a charged-device model (CDM). The ESD protection circuit includes a bipolar junction transistor (BJT). The BJT has a first end coupled to an input end of an input buffer and an output end of an output buffer. A second end of the BJT is coupled to a first ground rail. A control end of the BJT is coupled to one of a first power rail, a second power rail, the first ground rail and a second ground rail.