Provided is a semiconductor device capable of suppressing increase in size of a package and adjusting an amount of negative feedback. A power module as a semiconductor device includes an IGBT which is a switching element and a free wheel diode (FWD) parallelly connected to the switching element. The IGBT has, on a surface thereof, an emitter electrode and a gate electrode of the IGBT and a conductive pattern insulated from the emitter electrode and the gate electrode. The FWD has, on a surface thereof, an anode electrode of the FWD and a conductive pattern insulated from the anode electrode.

In accordance with an embodiment, a method includes using a monitoring circuit disposed on a monolithic integrated circuit to monitor an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit; using a time measuring circuit disposed on the monolithic integrated circuit to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, where the first drive signal is configured to cause a change of state of the first switching transistor; using an analysis circuit disposed on the monolithic integrated circuit to compare the measured first time delay with a first predetermined threshold to form a first comparison result; and indicating a first error condition based on the first comparison result.

A positive overshoot detection circuit comprises a transistor coupled to a current mirror, a reference current source coupled to the current mirror, and a comparator coupled to the reference current source and the current mirror. The comparator output indicates whether the current mirror's current is greater than the reference current source's current. A control input and a current terminal of the transistor are coupled to a clamping circuit. A negative overshoot detection circuit comprises a biasing sub-circuit coupled to a transistor, a resistor coupled to the transistor, and a comparator coupled to the transistor and the resistor. The comparator output indicates whether the transistor is in an on or off state. The biasing sub-circuit is coupled to a clamping circuit. In some implementations, the comparator outputs from the positive and negative overshoot detection circuits are provided to a driver circuit, which modifies its operation.

A system includes: 1) a buffer circuit; 2) circuitry coupled to an input of the buffer circuit; 3) a load coupled to an output of the buffer circuit; and 4) a clamp circuit coupled between an input of the buffer circuit and the output of the buffer circuit. The clamp circuit includes: 1) a bipolar junction transistor (BJT); 2) a first resistor with a first end coupled to a base terminal of the BJT and with a second end coupled to a collector terminal of the BJT; and 3) a second resistor with a first end coupled to the collector terminal of the BJT and with a second end coupled to the input of the buffer circuit. The second resistor is between an output of the circuitry and the input of the buffer circuit.

A positive overshoot detection circuit comprises a transistor coupled to a current mirror, a reference current source coupled to the current mirror, and a comparator coupled to the reference current source and the current mirror. The comparator output indicates whether the current mirror's current is greater than the reference current source's current. A control input and a current terminal of the transistor are coupled to a clamping circuit. A negative overshoot detection circuit comprises a biasing sub-circuit coupled to a transistor, a resistor coupled to the transistor, and a comparator coupled to the transistor and the resistor. The comparator output indicates whether the transistor is in an on or off state. The biasing sub-circuit is coupled to a clamping circuit. In some implementations, the comparator outputs from the positive and negative overshoot detection circuits are provided to a driver circuit, which modifies its operation.

To provide a semiconductor circuit capable of slightly generating inductance in two facing bus bars. Provided with a semiconductor circuit in which a collector-side bus bar 46 and an emitter-side bus bar 41 are arranged in parallel in a state of being isolated from each other and are fitted in a fixed manner to each other, and a inductance generation portion 411 is provided in one or both of the collector-side bus bar 46 and the emitter-side bus bar 41, the inductance generation portion 411 generating a difference in inductance between the collector-side bus bar 46 and the emitter-side bus bar 41.

Disclosed is an circuit for preventing latch-up, comprising a first transistor, a second transistor of a type opposite to that of the first transistor, and a control circuit, wherein a control terminal of the first transistor receives a first control voltage and a first terminal of the first transistor receives a first supply voltage; a control terminal of the second transistor receives a second control voltage, and is connected to a second terminal of the first transistor; a first terminal of the second transistor is connected to the control terminal of the first transistor, and a second terminal of the second transistor receives a second supply voltage. The control circuit is coupled on a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage for disconnecting the path when the first control voltage and/or the second control voltage is out of a predetermined range.

A power conversion device includes a power semiconductor switching device and a drive circuit. The power semiconductor switching device is configured to supply constant power to a load by switching and to be turned on and off by a control signal from an external control circuit. The drive circuit is configured to detect an operating temperature of the power semiconductor switching device and drive the power semiconductor switching device according to a result of the detection. The drive circuit includes a temperature detecting unit configured to receive the control signal from the external control circuit and detect the operating temperature of the power semiconductor switching device at timings according to the control signal.

A solenoid electrical diagnostic system includes a solenoid circuit operable in response to an electrical current. A low-side switch includes a low-side input configured to receive a pulsed voltage signal and a low-side output in signal communication with the solenoid circuit. The low-side switch continuously switches between an on-state and an off-state based on the pulsed voltage signal to adjust a level of the current flowing through the solenoid circuit. A solenoid monitoring unit generates a low-side output state signal based on an output voltage at the low-side output, and a low-side input state signal based on an input voltage at the low-side input. The solenoid electrical diagnostic system further includes an electronic hardware controller determines at least one operating condition of the solenoid circuit based on a comparison between the state signals and a threshold value.

A controller comprising a driver interface referenced to a first reference potential, a drive circuit referenced to a second reference potential, and an inductive coupling. The driver interface comprises a first receiver configured to compare a portion of signals having a first polarity on the first terminal of the inductive coupling with a first threshold, and a second receiver configured to compare a portion of signals having a second polarity on the second terminal of the inductive coupling with a third threshold. The drive circuit comprises a first transmitter configured to drive current in a first direction in the second winding to transmit first signals, and a second transmitter configured to drive current in a second direction in the second winding to transmit second signals, the second direction opposite the first direction.