A drive circuit includes: a signal generation circuit; a comparator; a comparator; and a short circuit determination unit. The signal generation circuit is configured to generate, as an output signal, a differential amplification signal of a voltage detection signal indicating a gate voltage of a semiconductor element and a delay signal of the voltage detection signal. The comparator is configured to compare a value of the differential amplification signal with a first reference voltage value. The comparator is configured to compare a voltage value indicating a gate current with a second reference voltage value. The short circuit determination unit is configured to determine whether or not the semiconductor element is in a short-circuited state, based on a result of comparison by each of the comparators, and generate a determination signal indicating a determination result.

A system includes a control circuit having first and second detectors coupled to a first node of the control circuit, first and second filters coupled to the first and second detectors, and a logic circuit coupled to the first and second filters, a diode circuit having a first node coupled to the first node of the control circuit, and a switch having a first current node coupled to a second node of the diode circuit, a gate coupled to a second node of the control circuit, and a second current node coupled to a third node of the control circuit, wherein a first detector is used to provide a first event overcurrent signal and a second detector is used to provide a multiple event overcurrent signal or a warning signal.

A method for protecting a power switch during turn-on includes sensing that a change in current through the power switch is in regulation, measuring a time the change in current through the power switch is in regulation, and comparing the time the change in current through the power switch is in regulation to a reference time. An over current signal, which can be used to disable the power switch, is generated if the time the change in current through the power switch is in excess of the reference time.

A controller for a semiconductor switch is described that includes a transmitter and a receiver that communicate across galvanic isolation using an inductive coupling. An example controller includes first circuitry referenced to a first reference potential, second circuitry referenced to a second reference potential and galvanically isolated from the first circuitry, and an inductive coupling galvanically isolating the first circuitry and the second circuitry. The inductive coupling includes a first winding referenced to the first reference potential and a second winding referenced to the second reference potential, wherein the first circuitry includes signal reception circuitry coupled to the inductive coupling, wherein the signal reception circuitry includes one or more signal receivers coupled to the first winding to receive signals transmitted over the inductive coupling.

A gate driver for driving a switching element includes turn-on current sources, turn-on switches, turn-off current sources, and turn-off switches. The turn-on current sources switch a voltage gradient of a rising edge waveform of a gate voltage of the switching element between a plurality of levels when the switching element is turned on. The turn-on switches drive and control the turn-on current sources. The turn-off current sources switch a voltage gradient of a falling edge waveform of the gate voltage between a plurality of levels when the switching element is turned off. The turn-off switches drive and control the turn-off current sources.

A semiconductor device, including a main switching element having a gate terminal and an emitter terminal, a sense switching element connected to the main switching element for detecting a current flowing through the main switching element, and a voltage division circuit connected between the gate terminal and the emitter terminal of the main switching element. The voltage division circuit includes a first resistor and a second resistor connected in series. A connection point of the first resistor and the second resistor is connected to the sense switching element, so that a voltage applied to the gate terminal of the main switching element is divided by the voltage division circuit, and a portion of the voltage is applied to the sense switching element.

A gate drive circuit includes a driver for driving a gate of a switching element, a peak voltage detector, and a drive capacity calculator. The peak voltage detector detects a peak voltage at a main terminal of the switching element when the switching element is OFF. The drive capacity calculator calculates a voltage difference value between the detected peak voltage and an allowable voltage value at the main terminal of the switching element, where the allowable voltage is based on the specifications of the switching element. The drive capacity calculator changes a drive capacity of the driver to gradually decrease the difference between the detected peak voltage and the allowable voltage.

Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper-main lead of the transistor, through the transistor, and from a lower-main lead of the transistor to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower-main lead to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower-control lead the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

A system includes a control circuit having first and second detectors coupled to a first node of the control circuit, first and second filters coupled to the first and second detectors, and a logic circuit coupled to the first and second filters, a diode circuit having a first node coupled to the first node of the control circuit, and a switch having a first current node coupled to a second node of the diode circuit, a gate coupled to a second node of the control circuit, and a second current node coupled to a third node of the control circuit, wherein a first detector is used to provide a first event overcurrent signal and a second detector is used to provide a multiple event overcurrent signal or a warning signal.

A positive overshoot detection circuit comprises a transistor coupled to a current mirror, a reference current source coupled to the current mirror, and a comparator coupled to the reference current source and the current mirror. The comparator output indicates whether the current mirror's current is greater than the reference current source's current. A control input and a current terminal of the transistor are coupled to a clamping circuit. A negative overshoot detection circuit comprises a biasing sub-circuit coupled to a transistor, a resistor coupled to the transistor, and a comparator coupled to the transistor and the resistor. The comparator output indicates whether the transistor is in an on or off state. The biasing sub-circuit is coupled to a clamping circuit. In some implementations, the comparator outputs from the positive and negative overshoot detection circuits are provided to a driver circuit, which modifies its operation.