A switch including a transistor to be protected, and a Miller effect protection unit including a protection transistor, the drain of the protection transistor being connected to the gate of the transistor to be protected, the source of the protection transistor being connected to the source of the transistor to be protected, a linking circuit, the linking circuit being a high-pass filter arranged between the gate of the protection transistor and the drain of the transistor to be protected, and a control circuit interposed between the gate of the protection transistor and the source of the transistor to be protected.

Circuits for protecting devices, such as gallium nitride (GaN) devices, and operating methods thereof are described. The circuits monitor a magnitude of the current in a device and reduce the magnitude of the current and/or shut down the device responsive to the magnitude of the current exceeding a threshold. These circuits safeguard devices from damaging operating conditions to prolong the operating life of the protected devices.

A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

A driver system operable to supply a drive signal to a motor includes a system input adapted to be coupled to an input voltage and a system output adapted to be coupled to the motor. The driver system includes a high-side transistor which has a first terminal coupled to the system input, a second terminal coupled to the system output, and has a control terminal. The driver system includes a low-side transistor which has a first terminal coupled to the system output, a second terminal coupled to a reference potential terminal, and has a control terminal. The driver system includes a low-side gate control circuit which provides a first level current responsive to a low-side digital control signal transitioning from a low state to a high state and provides a second level current if the output voltage is less than an upper reference voltage.

A vehicle powertrain includes an IGBT, having a Kelvin emitter and a mirror current sense, configured to energize an inductance, a first switch configured to draw a current from a gate of the IGBT at a rate based on a resistance engaged by the first switch while a current of the inductance exceeds a threshold, and a second switch configured to increase the rate in response to the current being less than the threshold. In one embodiment, the current is based on a filtered voltage across a resistor connected between the mirror current sense and chassis ground while the Kelvin emitter is connected to chassis ground. In another embodiment, the current is based on a filtered voltage across a resistor connected between the mirror current sense and the Kelvin emitter.

Methods and apparatuses for connecting multiple loads with a common return pin in engine control module application are disclosed. Only one of the multiple loads can be connected to a power source at a time. At the high side, each load is coupled to the power source through a respective pin at a connector. At the low side, the multiple loads share a common return pin at the connector that connects the loads to the ground. When a first load is connected to the power source at the high side, a first low side driver circuit is used to connect the first load to the ground at the low side. When a second load is connected to the power source at the high side, the second low side driver circuit is used to connect the second load to the ground at the low side.

System on a Chip (SoC) integrated circuits are configured to reduce Static Random-Access Memory (SRAM) power leakage. For example, SoCs configured to reduce SRAM power leakage may form part of an artificial reality system including at least one head mounted display. Power switching logic on the SoC includes a first power gating transistor that supplies a first, higher voltage to an SRAM array when the SRAM array is in an active state, and a third power gating transistor that isolates a second power gating transistor from the first, higher voltage when the SRAM array is in the active state. The second power gating transistor further supplies a second, lower voltage to the SRAM array when the SRAM array is in a deep retention state, such that SRAM power leakage is reduced in the deep retention state.

A vehicle powertrain includes an electric machine, an inverter including an IGBT having a gate configured to flow current through a phase of the electric machine, and a gate driver. The gate driver is configured to supply power onto the gate via a voltage regulated source, and in response to a collector current of the IGBT exceeding a previous steady state current through the phase, transition to a current regulated source to drive the gate. The gate driver may be configured to delay the transition by a predetermined time that is based on a difference between the previous steady state current and a reverse recovery peak current.

A switching element drive device that reduces a switching loss while suppressing noise with an inexpensive configuration, is provided. The switching element drive device includes a current sensor configured to measure a load current flowing through a load, a voltage sensor configured to measure an input voltage inputted from a power supply, and a control part configured to output a command value of a gate drive voltage to a gate drive voltage supply part, the gate drive voltage supply part being configured to supply the gate drive voltage for driving a switching element disposed between the power supply and the load, wherein the control part is further configured to determine the command value of the gate drive voltage based on the load current and the input voltage.

An inverter for an electric vehicle comprises a phase leg having series-connected upper and lower transistors between a positive bus and a ground bus. Upper and lower gate drive circuits supply gate drive signals to the upper and lower transistors. Each gate drive circuit includes an active clamp for deactivating the upper and lower transistors. The transistors are comprised of semiconductor devices, each having respective gate, collector, and emitter terminals. Each pair of gate and emitter terminals is adapted to provide an enhanced common source inductance therebetween. Each gate terminal is adapted to be tied to a ground voltage of the drive circuits. Each respective active clamp is comprised of a p-channel MOSFET having a source terminal connected to the gate terminal of a respective transistor and having a drain terminal connected to the emitter terminal of the respective transistor bypassing the respective enhanced common source inductance.