A radio frequency switch circuit includes a negative voltage generating circuit, a notch network, a logic control circuit, and a radio frequency switching circuit. The logic control circuit can be configured to, upon being driven by the negative voltage signal generated by the negative voltage generating circuit, control the operating modes of the radio frequency switching circuit; and the notch network is connected between the negative voltage generating circuit and the logic control circuit. As such, the influence of radio frequency signals generated by the radio frequency switching circuit can be filtered through the notch network, and the interference of radio frequency signals to the negative voltage generating circuit can be reduced, thereby improving the performance of the radio frequency switch circuit, for example in insertion loss, isolation and harmonic suppression.

A crossbar switch is disclosed having a first port, a second port, a third port, and a fourth port, the crossbar switch comprising: a first switching element coupled between the first port and the third port; a second switching element coupled between the first port and the fourth port; a third switching element coupled between the second port and the third port; and a fourth switching element coupled between the second port and the fourth port, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element are configured to couple only one of the first port and the second port to the third port, at any given time.

A switch comprising a first switching circuit assembly having a first pair of identical diodes in first anti-series configuration. The first switching circuit assembly constructed and arranged to cancel capacitance change wherein capacitance increases in a first diode of the first pair of identical diodes and, simultaneously, capacitance decreases in a second diode of the first pair of identical diodes with a first selectively applied radio frequency (RF) voltage input. The switch comprises a second switching circuit assembly having a second pair of identical diodes in second anti-series configuration. The second switching circuit assembly constructed and arranged to cancel capacitance change wherein capacitance increases in a first diode of the second pair of identical diodes and, simultaneously, capacitance decreases in a second diode of the second pair of identical diodes with a second selectively applied RF voltage input. A system and method are also provided.

A switch comprising a first switching circuit assembly having a first pair of identical diodes in first anti-series configuration. The first switching circuit assembly constructed and arranged to cancel capacitance change wherein capacitance increases in a first diode of the first pair of identical diodes and, simultaneously, capacitance decreases in a second diode of the first pair of identical diodes with a first selectively applied radio frequency (RF) voltage input. The switch comprises a second switching circuit assembly having a second pair of identical diodes in second anti-series configuration. The second switching circuit assembly constructed and arranged to cancel capacitance change wherein capacitance increases in a first diode of the second pair of identical diodes and, simultaneously, capacitance decreases in a second diode of the second pair of identical diodes with a second selectively applied RF voltage input. A system and method are also provided.

Apparatus and methods for providing hot-switching immunity for radio frequency switching circuits are disclosed. A radio frequency switching circuit may include both a mechanical switch and a solid-state switch. The mechanical switch may be configurable to couple an output path of a power amplifier to a subsequent component in its transmission path when in a first mechanical switch state and to decouple the output path of the power amplifier from the subsequent component when in a second mechanical switch state. The solid-state switch may be configurable to operatively decouple the mechanical switch from a radio frequency power source when in a first solid-state switch state but not when in a second solid-state switch state. The solid-state switch may be in the first solid-state switch state during transitions of the mechanical switch between the first and second mechanical switch states.

A switch assembly includes a PIN diode connected between an antenna port and a receive port, a first shunt FET device connected between the receive port and ground, a first series FET device connected between the antenna port and a transmit port, a second shunt FET device connected between the transmit port and ground, and a plurality of bias control contacts configured to receive a corresponding plurality of bias control voltages to forward bias the first shunt FET device and the first series FET device into an ON state and to reverse bias the PIN diode and the second shunt FET device into an OFF state in a transmit mode, and to reverse bias the first shunt FET device and the first series FET device into the OFF state and to forward bias the PIN diode and the second shunt FET device into the ON state in a receive mode.

An emission driver includes a latch circuit and a buffer circuit. The latch circuit receives a first signal, a second signal, and a first clock signal. The latch circuit includes a first output terminal and a second output terminal. The first output terminal of the latch circuit outputs a third signal according to the first clock signal. The second output terminal of the latch circuit outputs a fourth signal in reverse to the third signal according to the first clock signal. The buffer circuit includes a first input terminal, a second input terminal and a third output terminal. The first input terminal of the buffer circuit receives the third signal. The second input terminal of the buffer circuit receives the fourth signal. The third output terminal of the buffer circuit outputs an emission signal according to the third signal and the fourth signal.

An emission driver includes a latch circuit and a buffer circuit. The latch circuit receives a first signal, a second signal, and a first clock signal. The latch circuit includes a first output terminal and a second output terminal. The first output terminal of the latch circuit outputs a third signal according to the first clock signal. The second output terminal of the latch circuit outputs a fourth signal in reverse to the third signal according to the first clock signal. The buffer circuit includes a first input terminal, a second input terminal and a third output terminal. The first input terminal of the buffer circuit receives the third signal. The second input terminal of the buffer circuit receives the fourth signal. The third output terminal of the buffer circuit outputs an emission signal according to the third signal and the fourth signal.

A low-reflectivity solid-state switch circuit includes an input port configured to transmit an electronic signal and first and second output ports configured to receive the electronic signal. The switch circuit further includes a first switching element connected between the input port and the first output port, a second switching element connected between the input port and the second output port, a third switching element connected to a first conductive path between the first switching element and the first output port, and a fourth switching element connected to a second conductive path between the second switching element and the second output port. The third and fourth switching elements are utilizable to shunt current reflections from their connected conducted paths when the respective conductive path is configured in an off configuration.

A low-reflectivity solid-state switch circuit includes an input port configured to transmit an electronic signal and first and second output ports configured to receive the electronic signal. The switch circuit further includes a first switching element connected between the input port and the first output port, a second switching element connected between the input port and the second output port, a third switching element connected to a first conductive path between the first switching element and the first output port, and a fourth switching element connected to a second conductive path between the second switching element and the second output port. The third and fourth switching elements are utilizable to shunt current reflections from their connected conducted paths when the respective conductive path is configured in an off configuration.