A register and an analog-digital converter capable of detecting signal distortion in high-radiation environments are provided. The register includes: a signal input terminal receiving a digital signal; and a digital single event transient (DSET) detection unit detecting whether information of the digital signal input through the signal input terminal is distorted, wherein the DSET detection unit includes a first output terminal through which a first detection signal is output, the first detection signal being used to determine whether at least one of rising edge timing information and falling edge timing information of the digital signal is distorted.

A radiation hardened flip-flop includes a plurality of secondary flip-flops. Each secondary flip-flop includes both a data input terminal and an alternate data input terminal. Each secondary flip-flop also includes an enable terminal that selectively enables use of the alternate data input terminal. The radiation hardened flip-flop includes an error detection circuit that detects whether an error is present in one or more of the secondary flip-flops and provides an enable signal to the enable terminals indicating the presence or absence of an error in one or more of the secondary flip-flops.

Described herein is a method implemented by circuitry for providing fault tolerance in a combinational circuit. The circuitry identifies sensitive gates of the circuit that require protection from at least one of a first type of fault and a second type of fault. Further, circuitry computes for each first type of transistor included in the sensitive gate, a first failure probability, and for each second type of transistor included in the sensitive gate, a second failure probability. The circuitry calculates a first parameter corresponding to a number of the first type of transistors for which the computed first failure probabilities exceed a first predetermined threshold and a second parameter corresponding to a number of second type of transistors for which the computed second failure probabilities exceed a second predetermined threshold to determine a protection type based on an area overhead constraint.

This application relates to a bi-state driver circuit for switching an output terminal between a first predetermined voltage level and a high impedance state. The bi-state driver circuit comprises a first string of transistors connected between the output terminal and the first predetermined voltage level and comprising at least a first transistor arranged closer to the first predetermined voltage level and a second transistor arranged closer to the output terminal, a voltage divider circuit connected between the output terminal and a voltage level of a control signal attaining voltage levels between the first predetermined voltage level and a second predetermined voltage level, comprising at least one intermediate node having an intermediate voltage level between a voltage level of the output terminal and the voltage level of the control signal, and a second string of transistors connected between the intermediate node of the voltage divider circuit and the second predetermined voltage level, and comprising at least a third transistor. A control terminal of the second transistor is connected to the intermediate node. The first transistor is configured to be switched in accordance with the control signal. The third transistor is configured to be switched in accordance with the control signal, in a phase-locked relationship with the first transistor. The application further relates to a driver circuit for switching a first output terminal between a first output voltage level and a high impedance state, and for switching a second output terminal between a second output voltage level and the high impedance state. The application yet further relates to a method of controlling a bi-state driver circuit.

A circuit comprises a data storage element that includes a sampling stage configured to sample a data value, the sampling stage comprising a plurality of p-type devices, wherein at least one of the plurality of p-type devices is non-collinear relative to the other p-type devices, a plurality of n-type devices, wherein at least one of the plurality of n-type devices is non-collinear relative to the other n-type devices, a feedback stage configured to maintain the data value sampled by the sampling stage.

A tristate output buffer includes a first branch with a first buffer, and a second branch with a second buffer. The first buffer includes a supply port, a ground port, an output port, two switchable semiconductor elements of a first type, and two switchable semiconductor elements of a second type. Switching behavior of the switchable semiconductor elements of the first type differs from switching behavior of the switchable semiconductor elements of the second type. The two switchable semiconductor elements of the first type are connected in series and are between the supply port and the output port such that they can be put in a conductive state independent of each other. The two switchable semiconductor elements of the second type are connected in series and are between the ground port and the output port such that they can be put in a conductive state independent of each other.

A single event upset (SEU) hardened flip-flop comprises a master latch and a plurality of slave latches, where an output of the master latch is coupled to a respective input of the slave latches. A Muller element which has an input which is coupled to a respective output of the slave latches and an output which is coupled to a bus keeper. The bus keeper maintains a logic level output in presence of the SEU.

A single event upset (SEU) mitigation system is disclosed herein. The SEU system includes a trigger circuit configured to receive an input signal, a hold circuit operatively coupled to the trigger circuit and configured to receive a first signal from the trigger circuit, a reset circuit operatively coupled to the hold circuit and configured to output a reset signal in response to receiving one or more hold signals from the hold circuit, and a controller operatively coupled to the reset circuit, the controller configured to reset in response to the reset signal.

According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

The invention relates to devices and methods of maintaining the current starved delay at a constant value across variations in voltage and temperature to increase the speed of operation of the sequential logic in the radiation hardened ASIC design.