A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

This document discusses, among other things, apparatus and methods for an edge rate driver for a power converter switch. In an example, the driver can include an input node configured to receive a pulse width modulated signal, a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state, a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state, and a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch.

A semiconductor device may include a data output circuit and control signal output circuit. The data output circuit may convert a first input signal and a second input signal sequentially inputted thereto into output data and may compare the first and second input signals with a storage datum to generate a first comparison signal and a second comparison signal. The control signal output circuit may detect logic levels of bits included in the first and second comparison signals to generate a first detection signal and a second detection signal, may generate a first flag signal and a second flag signal from the first and second detection signals in response to a storage flag signal, and may sequentially output the first and second flag signals as transmission control signals.

A method of controlling and maintaining a constant slew rate at an output of a buffer is provided. The method includes the following steps: (a) receiving, (i) a first input signal and (ii) at least one of a control voltage using the buffer; (b) generating a threshold voltage using a first reference voltage generator; (c) comparing (i) the threshold voltage with an output of the buffer using at least one of a comparator; (d) determining a phase difference using a phase detector; (e) producing a DC voltage using a loop filter; (f) generating a reference voltage; (g) receiving the DC voltage and the reference voltage using an amplifier; (h) amplifying the difference between (a) said DC voltage, and (b) the reference voltage to obtain a control voltage using the amplifier; and (i) feeding the control voltage to the buffer.

A device includes a transistor cascode circuit including a first transistor configured to pull up voltage of a bulk and a node in response to a first control signal, and a second transistor configured to pull up voltage of an interface (I/O) pin in response to a second control signal. The device further includes a third transistor configured to pull down voltage of the I/O pin in response to a third control signal, and a feedback circuit configured to turn off the first transistor when the voltage of the I/O pin is above a predetermined level during a failsafe period.

As disclosed herein, a level shift circuit includes devices that are responsive to an ESD signal for placing those devices in a specific condition in response to the ESD signal indicating an ESD event. In some embodiments, the devices are transistors in current paths that are placed in a condition such that during an ESD event, voltage differentials in the current paths across voltage domain boundaries do not damage the circuitry of the level shift circuit. In some embodiments, some of the same devices that are responsive to the ESD event are also responsive to a signal to that detects the absence of a power supply voltage of one of the domains and places those devices in a condition to disable the level shift circuit if the power supply voltage is not present.

A sensor output circuit is limited with high accuracy, and reduces radio wave radiation by signal transmission using a single-line signal. The sensor output includes a pulse signal Vin that changes according to a physical quantity to be measured, MOS transistors that perform on/off operations according to the pulse signal Vin, a constant current source that generates a constant current, a MOS transistor which generates a gate voltage of a MOS transistor, MOS transistors which form a current mirror circuit, and the MOS transistor which works to maintain a drain voltage of the MOS transistor at a constant voltage, and the output terminal which is driven by the MOS transistors connected in series. In addition, an output signal from the sensor output circuit is transmitted to a control circuit via an output signal line. The control circuit includes a pull-up resistor, a capacitor, and an input gate circuit.

An off chip driver circuit includes a first power rail, a second power rail, an input/output pad, a pull-up circuit, a pull-down circuit. The pull-up circuit is configured to selectively activate at least one of charging paths between the first power rail and the input/output pad. The pull-up circuit includes a first resistor and PMOS transistors arranged on the charging paths, and the first resistor is coupled between the first power rail and the PMOS transistors. The pull-down circuit is configured to selectively activate at least one of discharging paths between the second power rail and the input/output pad. The pull-down circuit includes a second resistor and NMOS transistors arranged on the discharging paths, and the second resistor is coupled between the second power rail and the NMOS transistors.

A switch including multiple current branches and slope circuitry. The slope circuitry activates or deactivates the current branches one at a time according to a corresponding one of multiple slope functions in response to a transition of the input signal. Each current branch develops a current so that the output node follows a predetermined voltage-current function. Each slope function is other than a step function and may be linear or non-linear. A slope function may be configured as a current-starved inverter charging or discharging a capacitor with a fixed current. Delay circuitry may be included to delay the inputs or the outputs of the slope circuitry configured as multiple slope control circuits. The slope control circuits may be daisy-chained from first to last to effectuate the delay. Each current branch may include an electronic switch and may further include a resistor to determine the current level.

An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.