A noise tolerant buffer circuit, configured to interface a controller to a switching device, that includes an input, a first buffer, a second buffer, an output, and a switching device. The input provides a control signal to the first buffer cell input. The first buffer cell processes the control signal to generate a second buffer output. The second buffer cell processes the output of the first buffer to generate a second buffer output. The switching device is configured to receive an output of the second buffer and perform a switching operation based on the output of the second buffer. The switching operation generates noise that couples back to the first buffer cell and the second buffer cell, and the noise is divided between the first buffer cell and a second buffer to thereby reduce the noise to a value that does not trigger the first buffer or the second buffer.

Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., −25° C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.

A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

A semiconductor device includes a first conductivity-type substrate, and a cell region including: a second conductivity type deep well; first and second non-deep wells having the second conductivity-type, the first and second non-deep wells being in corresponding first and second portions of the substrate, the first and second portions of the substrate being in the deep well; and first, second, third and fourth transistor-regions. The first and second transistor-regions are correspondingly in the first and second non-deep wells and include first conductivity-type first transistors. The third and fourth transistor-regions are in the third and fourth portions of the substrate which are in the deep well, and include second transistors having the second conductivity-type. The first transistor-region is configured for a first power domain. The second, third and fourth transistor-regions are configured for a second power domain that is different than the first power domain.

A control circuit for controlling a data input/output is provided. The control circuit comprises a plurality of control level circuits that include a first control level circuit and a last control level circuit. Each control level circuit has a control element, with a number of control elements of the last control level circuit being greater than a number of control elements of the first control level circuit. Each control element is configured to receive a first control signal and a second control signal, and controls a current for the data input/output depending on the first and second control signals. The control circuit is configured to provide the first control signal to the control elements in a sequence starting at the first control level circuit and ending at the last control level circuit, and then to provide the second control signal to the last control level circuit in reverse order.

Structure and functionality reduce differential leakage current and compensate for differential capacitance discharge current from diode configurations to mitigate differential output polarity reversal that may occur in driver circuits. In an example driver circuit, one of two current sources coupled between a supply voltage and one output node is disabled during a driver disable time period (t.sub.pz) while the other continues to operate during a pre-charge monopulse time period (t.sub.d) within t.sub.pz. A third current source on the other side of the driver circuit and coupled to ground is also disabled during t.sub.pz. During t.sub.d, the following components are enabled: a charge current source coupled between the supply voltage and a second output node; a pair of current switches respectively coupled to the output nodes; and a pair of pull-down switches respectively coupled to control terminals of the current switches. After t.sub.pz, during a compensation time period (t.sub.comp), the current sources enabled during to are disabled and a compensation current source is enabled. After t.sub.comp, the compensation current source is disabled.

Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.

A sensor output circuit is limited with high accuracy, and reduces radio wave radiation by signal transmission using a single-line signal. The sensor output includes a pulse signal Vin that changes according to a physical quantity to be measured, MOS transistors that perform on/off operations according to the pulse signal Vin, a constant current source that generates a constant current, a MOS transistor which generates a gate voltage of a MOS transistor, MOS transistors which form a current mirror circuit, and the MOS transistor which works to maintain a drain voltage of the MOS transistor at a constant voltage, and the output terminal which is driven by the MOS transistors connected in series. In addition, an output signal from the sensor output circuit is transmitted to a control circuit via an output signal line. The control circuit includes a pull-up resistor, a capacitor, and an input gate circuit.