A physically unclonable function (PUF) comprises a plurality of conductors, at least some of which are arranged so that they interact electrically and/or magnetically with one another. A media surrounds at least of portion of each of the conductors and further defines at least one cavity, where the cavity is structured to provide the device with an environmentally dependent characteristic. Circuitry applies an electrical challenge signal to at least one of the conductors and receives an electrical output from at least one of the other conductors to generate an identifying response to the challenge signal that is unique to the device.

The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode. The single-end CMOS circuit may be configured to a process low-speed data transmission in the single-end CMOS input mode.

A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.

An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

A voltage level shifter device an input stage and an output stage. The input stage is configured to lower one of the first and second output terminals to the low level according to the level of the input voltage. A latch circuit includes a first branch having a first PMOS transistor and a second PMOS transistor coupled in series coupled between a shifted-high-level voltage supply terminal and the first output terminal and a second branch having a third PMOS transistor an a fourth PMOS transistor coupled in series between the shifted-high-level voltage supply terminal and the second output terminal. The first output terminal is a gate of the second PMOS transistor and to a gate of the third PMOS transistor. The second output terminal is coupled a gate of the fourth PMOS transistor and to a gate of the first PMOS transistor.

The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.

A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

A circuit and method are provided to monitor a clock for a data processor. The method includes receiving a clock signal and producing a first voltage proportional to a frequency of the clock signal. The first voltage is converted to a digital signal. During an initialization mode, the method ensures the clock signal is at a desired frequency and scales the digital signal using a first configurable ratio to produce a high threshold value. When changing from the initialization mode to an operating mode, the method ceases to scale the digital signal and maintains the high threshold value. During the operating mode, the method compares the digital signal to the high threshold value to determine if the clock signal has been increased in frequency beyond a desired level, and if so, triggers an overclock alert to a system management circuit of the data processor.

A potential generating circuit includes a first transistor and a second transistor. Potential at a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the potential generating circuit. Potential at a substrate of the second transistor varies with the first parameter. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as a first output of the potential generating circuit. A gate of the second transistor is connected to a drain of the second transistor. The substrate of the second transistor serves as a second output of the potential generating circuit.