A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.

A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

Reduced delay and improved threshold tracking over PVT in a comparator input circuit and comparator are provided by circuits that include an inverter stage having a first complementary pair of transistors connected in a push-pull configuration. An input of the inverter stage is coupled to the gates of the first complementary pair of transistors, and an output of the inverter is coupled to the drains of the first complementary pair of transistors. The circuits also include one or more first degeneration transistors coupled between a source of one of the first complementary pair of transistors and a power supply rail of the circuit, and a reference circuit with an output coupled to one or more gates of the first degeneration transistors. The reference circuit controls the one or more first degeneration transistors to cause the inverter stage to have a threshold voltage equal to a threshold control voltage.

Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

An analog circuit includes a logic output circuit and a standard cell. The logic output circuit outputs a first power supply voltage or a low-level signal to be an output signal. The standard cell includes at least two first-type transistors and at least two second-type transistors. The first-type transistors are connected in series. The first-type transistors receive a second power supply voltage, and output the second power supply voltage according to the output signal. A first voltage value of the first power supply voltage is less than a second voltage value of the second power supply voltage. The second-type transistors are connected in parallel, coupled to the first-type transistors at an output terminal, and output the low-level signal according to the output signal. First types of the first-type transistors are different from second types of the second-type transistors.