A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus.

Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

A shift register includes a first switch and a second switch coupled to a first node, a pull-down circuit selectively connecting the first node to a voltage end according to a potential of a second node, a control circuit, and an input stage circuit which may receive a previous-stage shift register output signal, a next-stage shift register output signal, and at least one scanning order logic signal. The first switch receives clock signals. A first output end of the input stage circuit outputs the previous-stage shift register output signal or the next-stage shift register output signal to a control end of the second switch based on the scanning order logic signal. The previous-stage shift register output signal or the next-stage shift register output signal triggers a second output end of the input stage circuit to output the scanning order logic signal to an input end of the control circuit.

An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.

A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

The present disclosure provides an integrated circuit and a computing system. The integrated circuit and a computing system includes a dynamic voltage and frequency scaling (DVFS) operation and a method of operating the integrated circuit. The integrated circuit includes a plurality of sub blocks and a dynamic voltage and frequency scaling (DVFS) controller. The DVFS controller is configured to output a workload of the plurality of sub blocks, determine a first frequency corresponding to the workload, determine a first voltage corresponding to the first frequency, and provide a second frequency among at least one frequency corresponding to the first voltage to the plurality of sub blocks.

Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.

An example apparatus includes: a current mirror having first and second outputs; oscillator circuitry including: a first transistor having a first terminal coupled to the first output of the current mirror, having a second terminal, and having a control terminal; and a second transistor having a first terminal coupled to the first output of the current mirror, having a second terminal coupled to the control terminal and the second terminal of the first transistor, and having a control terminal coupled to the second terminals of the first and second transistors; and current shunt circuitry having a terminal coupled to the second output of the current mirror.

A low pin count (LPC) bus serial interrupt system includes: an interrupt direction signal generator configured to determine a current interrupt direction signal according to whether a host currently sends a first interrupt signal to an external device; and a level-shifter configured to convert a voltage level of a signal exchanged between the host and the external device according to the current interrupt direction signal.