A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

An electronic device assembly includes a master device, and a plurality of peripheral devices. The master device includes a signal reading unit, a layer identification unit, and a selecting and controlling unit. The plurality of peripheral devices is coupled to the master device and connected one by one in series. The signal reading unit is configured to read layer signals from the plurality of peripheral devices, the layer identification unit is configured to identify a layer information of the plurality of peripheral devices according to the layer signals; and the selecting and controlling unit is configured to select and control one or more of the plurality of peripheral electronic devices according to the layer information.

An input buffer circuit that receives differential signals includes a first resistive path circuit, a second resistive path circuit and a feedback circuit. The first resistive path circuit may generate a first common mode voltage from the differential signals. The feedback circuit is coupled to the first resistive path circuit. The feedback circuit receives the first common mode voltage as an input. The second resistive path circuit includes a transistor circuit and a resistor formed in a serial circuit configuration. The second resistive path circuit may generate a second common mode voltage on a node formed between the transistor circuit and the resistor by controlling activation of the transistor circuit using outputs from the feedback circuit. The first common mode voltage may be substantially identical to the second common mode voltage.

A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

An input buffer includes a pair of input transistors and associated injection circuits. A first input transistor has a source coupled to a first voltage rail through a first current source and a gate coupled to a first wire of a multi-wire serial bus. Three or more resistors in a first injection circuit couple the wires of the serial bus to a first common node, which is coupled to the source of the first input transistor by a first capacitor. A second input transistor has a source coupled to the first voltage rail through a second current source and a gate coupled to a second wire of the serial bus. Three or more resistors in a second injection circuit couple the wires of the multi-wire serial bus to a second common node, which is coupled to the source of the second input transistor by a second capacitor.