A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

A resistance of configurable termination circuitry located at an interface between a memory component and a processing device is adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistance of the configurable termination circuitry is adjusted based on a mode of the configurable termination circuitry.

A control device of a power switch includes a voltage boost circuit, a discharge circuit and a bias voltage generating circuit. The voltage boost circuit generates a control voltage at a control end of the power switch by boosting a base voltage. The discharge circuit provides a discharge path between the control end of the power switch and a reference ground end according to a bias voltage. The bias voltage generating circuit compares an output voltage on an output end of the power switch with the control voltage to generate a comparison result, and generates the bias voltage according to the comparison result.

A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.

An integrated circuit (IC) includes a level shifter coupled to receive a first supply voltage and a second supply voltage and configured to generate a first output signal and a second output signal in response to an input command signal and an edge detector configured to detect an edge on the second supply voltage and to sink a current from the level shifter in response to detection of the edge in order to prevent a change in logic state of the first output signal or the second output signal. The edge detector can include a positive edge detector configured to generate a positive edge signal in response to detection of a positive going edge of greater than a first predetermined slew rate and a negative edge detector configured to generate a negative edge signal in response to detection of a negative going edge of greater than a second predetermined slew rate.

A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.

A level shifter includes a signal generator that generates differential signals on a first output and a second output. A first capacitor is coupled between the first output and a first node and a second capacitor is coupled between the second output and a second node. A third capacitor is coupled between the first node and a first voltage potential, wherein the capacitance of the third capacitor is variable. A fourth capacitor is coupled between the second node and the first voltage potential, wherein the capacitance of the fourth capacitor is variable.

Provided is a level shift circuit capable of avoiding breakdown due to level shift operation. The level shift circuit includes: a floating power supply having one end connected to an output terminal; a circuit configured to receive a voltage of the floating power supply, a voltage of a low level power supply and first and second pulse signals from a pulse generating circuit, thereof to output first and second signals; and a logic circuit configured to receive first and second signals, thereby converting a signal that is input to the pulse generating circuit into a signal that fluctuates between a voltage at the one end of the floating power supply and a voltage at the other end thereof to output the converted signal.

According to one embodiment, a semiconductor device includes first, second, third, and fourth circuits. A first voltage is applied to the first circuit. A second voltage is applied to each of the second, third and fourth circuits. The third circuit is configured to generate a first control signal and a second control signal based on a signal generated by the first circuit and a signal generated by the second circuit. The fourth circuit is configured to output an output signal based on the first control signal and the second control signal. The output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied.

This application describes methods and apparatus for selectively clamping a signal path (106) for an analogue audio signal to a clamp voltage, e.g. ground. Voltage clamping circuitry (200) is disclosed having a first switching device (201) in series with a second switching device (202) between a node of the signal path and the clamp voltage. The clamping circuitry is configured to be operable in: a first state where the first and second switching devices are both on to electrically connect the signal path to the clamp voltage; and also a second state to electrically disconnect the signal path from the clamp voltage. In the second state one of the first and second switching devices is configured to block conduction when the voltage at said node of the signal path is positive and the other switching device is configured to block conduction when the voltage at said node of the signal path is negative.