Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD−X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

Disclosed is a control circuit for protecting MOSFETs in I/O buffers or other devices from overvoltage damage, especially during power ramp up. The control circuit can perform additional functions. In one embodiment an integrated circuit (IC) includes input/output (I/O) buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage Vddio. Each of the I/O buffers has a bias voltage generator that is configured to generate a first bias voltage with a magnitude that depends on a control signal; an output stage that receives the first bias voltage, wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer. The IC also includes an I/O buffer controller coupled to the I/O buffers and configured to generate the control signal based upon a magnitude of the output supply voltage Vddio.

An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.

A resistance of configurable termination circuitry located at an interface between a memory component and a processing device is adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistance of the configurable termination circuitry is adjusted based on a mode of the configurable termination circuitry.

A semiconductor product being convertible or converted from a customizable configuration into a selectable or selected one of a plurality of different customized configurations, wherein the semiconductor product comprises a customizing unit configured for customizing the semiconductor product into one of the customized configurations selected by a received customizing data structure specifying a selected application of the semiconductor product, and a plurality of functional blocks each configured for providing an assigned functionality and all being deactivated when the semiconductor product is not in one of the customized configurations, wherein the customizing unit is configured for activating only a subgroup of the functional blocks based on the received customizing data structure.

On-die termination (ODT) is triggered through a serial signal encoding on an ODT signal line instead of a simple binary enable signal. An ODT circuit applies one of multiple termination impedances based on the ODT signal encoding. An ODT enable signal line receives an ODT enable signal as multiple serial bits to encode the selected termination impedance, to cause the ODT circuit to apply the selected termination impedance.

The off-chip driving (OCD) device includes a signal transition detector, a front-end driver, a first main driver, a second main driver, a first resistance provider and a second resistance provider. The signal transition detector is used to detect a transition status of an input signal to generate decision information. The front-end driver generates control signals according to the decision information, and generates driving signals according to the input signal. The first main driver and the second main driver generate an output signal to a pad according to the driving signals. The first resistance provider adjusts a first resistance between the first main driver and the pad according to a first control signal. The second resistance provider adjusts a second resistance between the second main driver and the pad according to a second control signal.

An ultrasound imaging device includes a plurality of ultrasound transducers arranged in an array of rows and columns. Each of the transducers has a first electrode and a second electrode. The first electrodes of the transducers of a same row are interconnected and the second electrodes of the transducers of a same column are interconnected.