Systems, methods, and computer program products for protecting circuits are provided. Aspects include receiving, by a processing element, a feedback signal, the feedback signal taken from an output of a circuit, determining a range of expected feedback values, comparing the feedback signal to the range of expected feedback values, and based at least in part on determining that the feedback signal is outside the range of expected feedback values for a first length of time, disabling the circuit.

An input/output circuit includes a logic unit configured to generate a first signal and a second signal based on data and a first control signal, a driver including a first PMOS transistor having a first gate, a first source that receives a first voltage from a first voltage source, and a first drain, and a first NMOS transistor having a second gate that receives the second signal, a second source that receives a second voltage from a second voltage source less than the first voltage, and a second drain connected to the first drain, a gate-tracking circuit configured to receive the first signal and transfer the received first signal to the first gate of the first PMOS transistor based on a second control signal, and an input/output terminal connected to the first drain and the second drain.

The present invention relates to a system comprising glasses (101), a communication unit (103) and a cable (102), whereby the cable comprises two galvanic connections adapted for transporting power and bidirectional data traffic, whereby the glasses and the communication unit are arranged for multiplexing a plurality of outgoing data streams into a multiplexed data stream to be transmitted over said cable and arranged for receiving an incoming data stream and demultiplexing said incoming data stream into separate data streams, and whereby said communication unit (103) is arranged for being connected wired or wirelessly to an external processing device (201), preferably the external processing device being a smartphone.

A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the second IC chip comprises a hard macro having an input data associated with the output data for the logic operation.

The present disclosure relates to a solid-state imaging apparatus, a method for driving the solid-state imaging apparatus, and electronic equipment for improving the determination speed of comparators and allowing the comparators to operate faster. A differential input circuit operates on a first power supply voltage and outputs a signal when a voltage of a pixel signal is higher than a voltage of a reference signal. A voltage conversion circuit converts the output signal from the differential input circuit into a signal corresponding to a second power supply voltage. A positive feedback circuit accelerates a transition rate at which a comparison result signal of a comparison in voltage between the pixel signal and the reference signal is inverted. Multiple time code transfer sections each include a shift register that transfer a time code. The present disclosure can be applied, for example, to an imaging apparatus including A/D converters disposed in pixels.

In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

A voltage level translator translates signals between first and second voltage domains. An output buffer for a channel thereof includes a first plurality of PFETs and a first plurality of NFETS that are coupled to provide staggering of the output signal. A supply difference sensing circuit can disable staggering when an input voltage supply is greater than or equal to a VCCI trigger for the output voltage supply.

A data interface is disclosed, which includes an electrostatic discharge circuit, and a charge transmitting circuit connected to a binding wire through the electrostatic discharge circuit; the charge transmitting circuit includes a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire. According to the data interface, charges in a charging capacitor and a parasitic capacitor are redistributed, which could not only reduce a power consumption loss caused by a parasitic capacitor in a communication channel but also effectively reduce time delay. In addition, the use of dual-wire communication is avoided by using single-wire communication, and the manufacturing costs are reduced relative to low-voltage differential signaling (LVDS).

One or more embodiments are directed to inter-integrated circuit (I2C) transmitters, receivers, and devices that utilize a stable reference voltage for driving a pre-driver of the transmitter and for driving a first input stage of the receiver. One embodiment is directed to a device A device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage.

A device comprising transistors in a series connection is disclosed. In an embodiment a device includes a first transistor, a second transistor connected to the first transistor and a third transistor connected to the second transistor, wherein the transistors are connected in a series connection, and wherein the third transistor is configured to be controlled by a digital signal.