Patent classifications
H03K19/082
Ternary logic element and ternary logic system including same
A ternary logic element including a transistor and a switching element. The transistor includes a channel layer including silicon, an input electrode, an output electrode, and a control electrode. The switching element includes an emitter, a base extending from the emitter, and a collector extending from the base. When a first control voltage is applied to the control electrode, the ternary logic element outputs a first voltage, and when a second control voltage different from the first control voltage is applied to the control electrode, the ternary logic element outputs a second voltage different from the first voltage, and when a third control voltage different from the first control voltage and the second control voltage is applied to the control electrode, the ternary logic element outputs a third voltage different from the first voltage and the second voltage.
BLANKING PERIODS FOR SAFELY EXECUTING EXTERNAL TRISTATE REQUESTS
This disclosure is directed to systems, circuits, and techniques for controlling a power switch and for executing tristate requests. Controlling a power switch may comprise delivering drive signals from a driver circuit to the power switch to control ON/OFF switching of the power switch, wherein an ON signal causes a charge period followed by an ON period for the power switch and wherein an OFF signal causes a discharge period followed by an OFF period for the power switch; and receiving an external tristate request to place the driver circuit into a tristate. The driver circuit may immediately enter the tristate in response to the tristate request being received during the ON period or the OFF period, whereas the driver circuit may wait for completion of a tristate blanking period prior to entering tristate in response to the tristate request being received during the charge period or the discharge period.
Blanking periods for safely executing external tristate requests
This disclosure is directed to systems, circuits, and techniques for controlling a power switch and for executing tristate requests. Controlling a power switch may comprise delivering drive signals from a driver circuit to the power switch to control ON/OFF switching of the power switch, wherein an ON signal causes a charge period followed by an ON period for the power switch and wherein an OFF signal causes a discharge period followed by an OFF period for the power switch; and receiving an external tristate request to place the driver circuit into a tristate. The driver circuit may immediately enter the tristate in response to the tristate request being received during the ON period or the OFF period, whereas the driver circuit may wait for completion of a tristate blanking period prior to entering tristate in response to the tristate request being received during the charge period or the discharge period.