According to one embodiment, an integrated electronic circuit has a switching network configured to receive binary control states, one or more secret-carrying gates, wherein each secret-carrying gate represents Boolean secrets and is configured to receive binary input states and to output one or more Boolean secrets according to a state sequence of the binary input states, and one or more flip-flops configured to store binary output states output by the switching network and to supply binary input states to the one or more secret-carrying gates based on the stored binary output states. The switching network generates the binary output states by combining the binary control states and Boolean secrets output by the one or more secret-carrying gates. The integrated electronic circuit outputs Boolean secrets from the one or more secret-carrying gates and/or the binary output states from the switching network to another integrated electronic circuit.

An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.

An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.

Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

A hearable has an audio amplifier circuit coupled to a speaker as a load. The amplifier circuit has current source drive, which attenuates electromagnetically coupled noise of the speaker. In other instances, the amplifier circuit has a first amplifier mode and a second amplifier mode, wherein in the first amplifier mode the amplifier circuit becomes configured to drive the speaker as a voltage source, and in the second amplifier mode the amplifier circuit becomes configured to drive the speaker as a current source. Control logic varies the amplifier circuit between i) the first amplifier mode for larger amplitudes of the audio signal, and ii) the second amplifier mode for smaller amplitudes of the audio signal. Other aspects are also described and claimed.

A hearable has an audio amplifier circuit coupled to a speaker as a load. The amplifier circuit has current source drive, which attenuates electromagnetically coupled noise of the speaker. In other instances, the amplifier circuit has a first amplifier mode and a second amplifier mode, wherein in the first amplifier mode the amplifier circuit becomes configured to drive the speaker as a voltage source, and in the second amplifier mode the amplifier circuit becomes configured to drive the speaker as a current source. Control logic varies the amplifier circuit between i) the first amplifier mode for larger amplitudes of the audio signal, and ii) the second amplifier mode for smaller amplitudes of the audio signal. Other aspects are also described and claimed.

A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.