An Ethernet network is composed of one or more network infrastructure devices, such as a hubs, repeaters, switches or routers, which provides data interconnection and may provide operational power, or some part thereof, to remote network data terminal equipment such as a wireless access point, IP telephone, IP camera or network end station. Most Ethernet networks operate over a combination of the pairs in an unshielded twisted pair (UTP) or shielded twisted pair (STP) cable, or in some cases may operate over fiber optic cables. The individual links of Ethernet network, between the network infrastructure device and the Data Terminal Equipment (DTE) may be able to operate at one or more data rates such as 10 Mb/s, 100 Mb/s, 1 Gb/s, 2.5 Gb/s, 5 Gb/s and 10 Gb/s, or any combination thereof. The invention discloses an Ethernet Physical Layer (PHY) circuit, in combination with an Integrated Connector Module (ICM), which may reside inside the network equipment at either end of the Ethernet link. The combined PHY-ICM physical layer network device provides the appropriate encoding/decoding and signaling to operate over the specific network cable medium at the required data rate(s). The electrical and mechanical design of the combined PHY-ICM enables a modular approach such that during final assembly, the PHY-ICM can be optimized for operation over the appropriate data rate(s), whether it supports the provision of operational power between the network equipment, and if so at what power level, as well as other functionality. Furthermore, the PHY-ICM is designed to maintain a common electrical and mechanical footprint regardless of which of the features are included or excluded, to optimize the system cost for a specific maximum data rate, as well as minimize any re-engineering necessary on the part of the network equipment designer.

This application provides decompression circuits. An example decompression circuit includes a plurality of sub-circuits. The sub-circuit includes a plurality of cellular automaton (CA) circuits and a phase shifter. Each of the plurality of CA circuits includes a first XOR circuit and a register. The first XOR circuit includes a first input end, a second input end, and an output end. A data input end of the register is coupled to the output end of the first XOR circuit. A data output end of the register is coupled to the first input end of the first XOR circuit and an input end of the phase shifter. The data output end of the register is further coupled to the second input end of the first XOR circuit in a different CA circuit. The phase shifter is configured to output a test signal.

An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

A memory system includes a stacked memory device and a controller. The stacked memory device includes a base die and a plurality of memory dies stacked on the base die. Each of the plurality of memory dies has a plurality of channels, and the base die is configured to function as an interface for transmitting signals and data of the pluralities of channels. The controller controls the stacked memory device such that first and second data move control operations are sequentially performed to transmit moving data from a target channel of the pluralities of channels to a destination channel of the pluralities of channels. The first data move control operation is performed to store the moving data in the target channel into the base die, and the second data move control operation is performed to write the moving data stored in the base die into the destination channel.

A transmitter includes a driving circuitry configured to drive a channel coupled to an output node by controlling an output impedance of a pull-up path, an output impedance of a pull-down path, or both, according to one or more multi-bit data signals, a pull-up control signal, and a pull-down control signal; a driving control circuit configured to generate the pull-up control signal and the pull-down control signal according to one or more calibration signals and the multi-bit data signals or according to the calibration signals and one or more duplicate multi-bit data signals, the duplicate multi-bit data signals duplicating the multi-bit data signals; and a look-up table storing values of the calibration signals.

A transmitter includes a driving circuitry configured to drive a channel coupled to an output node by controlling an output impedance of a pull-up path, an output impedance of a pull-down path, or both, according to one or more multi-bit data signals, a pull-up control signal, and a pull-down control signal; a driving control circuit configured to generate the pull-up control signal and the pull-down control signal according to one or more calibration signals and the multi-bit data signals or according to the calibration signals and one or more duplicate multi-bit data signals, the duplicate multi-bit data signals duplicating the multi-bit data signals; and a look-up table storing values of the calibration signals.

A field programmable device or software-defined hardware can change its functions by using software codes to alter the routing path of interconnect signal lines or the electrical properties of fundamental building elements. The field programmable device includes I/O interface blocks and signal processing blocks comprising analog signal processing units, digital signal processing units, memory units, clock units, and other supporting functional units which are electrically connected by user programmable interconnect signal lines. The analog signal processing functions can be altered by changing the electrical properties of fundamental building elements as well as the programmable signal lines after the device is manufactured.

A reversible logic circuit and an operation method thereof are provided. The logic circuit includes resistive switching cells, word lines, and bit lines. The word lines and the bit lines are perpendicular to each other. The anode of a resistive switching cell is connected to the word line as a first input terminal to apply logic operating voltage or be grounded. The cathode of a resistive switching cell is connected to the bit line as a second input terminal to apply logic operating voltage or be grounded. When performing reversible logic operation, four levels of resistance states of the resistive switching cell are used as logic outputs to implement single-input NOT and dual-input C-NOT reversible logic functions.

Some embodiments include a system comprising: an RF source configured to generate an RF signal; an RF frequency control circuit coupled to the RF source and configured to adjust a frequency of the RF signal; an accelerator structure configured to accelerate a particle beam in response to the RF signal; and control logic configured to: receive a plurality of settings over time for the RF source; adjust the RF signal in response to the settings; and adjust a setpoint of the RF frequency control circuit in response to the settings.

The present disclosure describes a power supply switch that includes a voltage generator, a switch circuit, and a confirmation circuit. The voltage generator is configured to compare a first power supply voltage to a second power supply voltage and to output the first power supply voltage or the second power supply voltage as a bulk voltage (V.sub.bulk). The switch circuit includes one or more transistors and is configured to (i) bias bulk terminals of the one or more transistors with the V.sub.bulk and (ii) output either the first power supply voltage or the second power supply voltage as a voltage output signal. The confirmation circuit is configured to output a confirmation signal that indicates whether the voltage output signal transitioned from the first power supply voltage to the second power supply voltage.