An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data output contacts. The array of switch cells receives the control signals directly from the control signal contacts and response to the control signals by switchably interconnecting the data input contacts with selected ones of the data output contacts.

Superconducting output amplifiers with interstage filters and related methods are described. An example superconducting output amplifier includes a first superconducting output amplifier stage and a second superconducting output amplifier stage. The superconducting output amplifier may further include a first terminal for receiving a first single flux quantum (SFQ) pulse train and coupling the SFQ pulse train to each of the first superconducting output amplifier stage and the second superconducting output amplifier stage. The superconducting output amplifier may further include an interstage filter comprising a damped Josephson junction (JJ) coupled between the first superconducting output amplifier stage and the second superconducting output amplifier stage, where the interstage filter is arranged to reduce distortion in an output voltage waveform generated by the superconducting output amplifier in response to at least the first SFQ pulse train.

Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

One example includes a flux switch system. The system includes an input stage configured to provide an interrogation pulse. The system also includes a plurality of flux loops configured to receive an input current. Each of the flux loops includes a Josephson junction configured to trigger to generate an output pulse in response to a first polarity of the input current and to not trigger to generate no output pulse in response to a second polarity of the input current opposite the first polarity. The system further includes an output stage configured to propagate the output pulse to an output of the flux switch system.

Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

The present disclosure relates to a reciprocal quantum logic (RQL) inverter including an inverter bias tap, a pulse generating Josephson junction (JJ), and a superconducting quantum interference device (SQUID) based structure, which includes a SQUID JJ and is connected between the inverter bias tap and the pulse generating JJ. The SQUID based structure is configured to receive an inverter bias signal from the inverter bias tap and receive a data input from a previous circuit stage. When the data input is at logic state “0,” the pulse generating JJ can be triggered so as to provide an output signal with logic state “1.” When the data input is at logic state “1,” the first SQUID JJ can be triggered thereby preventing the pulse generating JJ from be triggered, such that the output signal is provided at logic state “0.”

Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm.

The present invention relates to an inductive dipole element for a superconducting microwave quantum circuit. The dipole element comprises a DC-SQUID formed by a pair of Josephson junctions shunted by an inductance, wherein the Josephson junctions have equal energy, and the Josephson junctions and the inductance are arranged such that each of the junctions forms a loop with the inductance. The two loops are asymmetrically threaded with external magnetic DC fluxes φ.sub.ext1 and φ.sub.ext2, respectively, such that φ.sub.ext1=π and φ.sub.ext2=0, wherein parametric pumping is enabled by modulating the total flux φ.sub.Σ=φ.sub.ext,1+φ.sub.ext,2 threading the dipole element, thereby allowing even-wave mixing between modes that participate in the dipole element with no Kerr-like interactions.

One example includes a superconducting latch system. The system includes a first input stage configured to receive a first input pulse and a second input stage configured to receive a second input pulse. The system also includes a storage loop configured to switch from a first state to a second state in response to receiving the first input pulse, and to switch from the second state to the first state in response to the second input pulse. The first state corresponds to no flux in the storage loop and the second state corresponds to a flux in the storage loop. The system further includes an output stage configured to generate an output pulse in the second state of the storage loop.

An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data output contacts. The array of switch cells receives the control signals directly from the control signal contacts and response to the control signals by switchably interconnecting the data input contacts with selected ones of the data output contacts.