The various embodiments described herein include methods, devices, and systems for implementing logic gates. In one aspect, a circuit includes: (1) a superconducting component having a plurality of alternating narrow and wide portions; (2) a plurality of heat sources, each heat source of the plurality of heat sources coupled to a corresponding narrow portion of the plurality of alternating narrow and wide portions and configured to selectively provide heat to the corresponding narrow portion; (3) a bias current source coupled to each narrow portion of the plurality of alternating narrow and wide portions; and (4) an output node adapted to output a respective current while the plurality of superconducting components is in the non-superconducting state.

The various embodiments described herein include methods, devices, and systems for implementing logic gates. In one aspect, a circuit includes: (1) superconducting components; (2) heat sources, each coupled to a corresponding superconducting component and configured to selectively provide heat to that component; and (3) a current source coupled to the superconducting components and configured to selectively provide: (a) a first current to bias the components such that combination of the first current and heat from any heat source causes the components to transition to a non-superconducting state; and (b) a second current to bias the components such that (i) combination of the second current and heat from each heat source causes the components to transition to the non-superconducting state, and (ii) a combination of the second current and heat from only a subset of the heat sources does not cause the components to transition to the non-superconducting state.

A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Large fan-in logical gate circuits for use in reciprocal quantum logic (RQL) systems and related methods permit for improved efficiency and density of RQL logic. A majority 3-of-5 gate circuit, as described, can be extended to include more than five inputs, and can also be modified to create AND gates, OR gates, and OA gates. The gate circuits can accommodate inputs and provide outputs each in the form of single flux quantum (SFQ) pulses, either positive or negative, to indicate asserted and de-asserted logic states, respectively.

A Josephson AND/OR gate circuit makes efficient use of Josephson junction (JJ) and inductor components to provide two-input, two-output AND/OR logical functions. The circuit includes four logical input storage loops that each contain one of two logical decision JJs that are configured such that they trigger to provide the OR and AND signals, respectively. Functional asymmetry is provided in the topologically symmetrical AND/OR gate circuit by a bias storage loop that includes both of the logical decision JJs and that is initialized to store a directional .sub.0 of current at system start-up.

An inverting reciprocal quantum logic (RQL) gate circuit has an input stage having a logical input asserted based on receiving a positive single flux quantum (SFQ) pulse and an output stage comprising phase mode logic (PML) inverter circuitry. The input stage includes one or more storage loops, at least one being associated with each logical input, each comprising an input Josephson junction (JJ), a storage inductor, and a logical decision JJ, the logical decision JJ being common to all the storage loops associated with the logical inputs and being configured to trigger based on biasing provided by one or more currents stored in the storage loops and a first bias signal provided to the input stage. The output stage de-asserts an output and is provided with a second bias signal having a second state opposite of a first state of the first bias signal.

An reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.

An electric circuit includes one or more photon detector components and a superconducting logic gate component coupled to respective outputs of the one or more photon detector components. The electric circuit further includes a bias source electrically coupled to the superconducting logic gate component, the bias source configured to provide a bias current adapted to cause the superconducting logic gate component to function as a logical gate. The electric circuit also includes an optical switch component electrically coupled to an output of the superconducting logic gate component.