Patent classifications
H03K19/1958
LOW POWER CRYO-CMOS CIRCUITS WITH NON-VOLATILE THRESHOLD VOLTAGE OFFSET COMPENSATION
Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.
Cryogenic-CMOS interface for controlling qubits
Systems and methods related to a cryogenic-CMOS interface for controlling qubit gates are provided. A system for controlling qubit gates includes a first device comprising a quantum device including qubit gates. The system further includes a second device comprising a control system configured to operate at the cryogenic temperature. The control system includes charge locking circuits, where each of the charge locking circuits is coupled to at least one qubit gate via an interconnect such that each of the charge locking circuits is configured to provide a voltage signal to at least one qubit gate. The control system further includes a control circuit comprising a finite state machine configured to provide at least one control signal to selectively enable at least one of the charge locking circuits and to selectively enable a provision of a voltage signal to a selected one of the charge locking circuit.
LOW POWER CRYO-CMOS CIRCUITS WITH NON-VOLATILE THRESHOLD VOLTAGE OFFSET COMPENSATION
Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.
Superconducting logic circuits
A device includes a plurality of superconducting components, each having a first terminal and a second terminal; a plurality of current sources, being electrically-connected to the first terminal of a corresponding superconducting component and configured to selectively provide a first current; and a bias current source electrically-connected to the respective first terminal of each of the plurality of superconducting components. The bias current source is configured to provide a second current adapted to bias the superconducting components such that (1) a combination of the second current and the first current from each current source causes the plurality of superconducting components to transition from the superconducting state to the non-superconducting state, and (2) a combination of the second current and the first current from each current source of only a subset of the plurality of current sources does not cause the plurality of superconducting components to transition to the non-superconducting state.
CRYOGENIC-CMOS INTERFACE FOR CONTROLLING QUBITS
Systems and methods related to a cryogenic-CMOS interface for controlling qubit gates are provided. A system for controlling qubit gates includes a first device comprising a quantum device including qubit gates. The system further includes a second device comprising a control system configured to operate at the cryogenic temperature. The control system includes charge locking circuits, where each of the charge locking circuits is coupled to at least one qubit gate via an interconnect such that each of the charge locking circuits is configured to provide a voltage signal to at least one qubit gate. The control system further includes a control circuit comprising a finite state machine configured to provide at least one control signal to selectively enable at least one of the charge locking circuits and to selectively enable a provision of a voltage signal to a selected one of the charge locking circuit,
CHARGE LOCKING CIRCUITS AND CONTROL SYSTEM FOR QUBITS
Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.
Superconducting Logic Circuits
A device includes a plurality of superconducting components, each having a first terminal and a second terminal; a plurality of current sources, being electrically-connected to the first terminal of a corresponding superconducting component and configured to selectively provide a first current; and a bias current source electrically-connected to the respective first terminal of each of the plurality of superconducting components. The bias current source is configured to provide a second current adapted to bias the superconducting components such that (1) a combination of the second current and the first current from each current source causes the plurality of superconducting components to transition from the superconducting state to the non-superconducting state, and (2) a combination of the second current and the first current from each current source of only a subset of the plurality of current sources does not cause the plurality of superconducting components to transition to the non-superconducting state.
SYSTEM AND METHOD FOR CONTROLLING SUPERCONDUCTING QUBITS USING SINGLE FLUX QUANTUM LOGIC
A system and method for controlling superconducting qubits is provided. In some aspects the method includes assembling, using a controller of a quantum computing system, a pulse subsequence that comprises pairs of voltage pulses timed symmetrically with respect to a period corresponding to a qubit frequency of a superconducting qubit in the quantum computing system. The method also includes generating, using the controller, a pulse sequence using a repetition of a pulse subsequence. The method further includes controlling the superconducting qubit by applying the pulse sequence to the superconducting qubit using a single flux quantum (SFQ) driver coupled thereto.
System and method for controlling superconducting qubits using single flux quantum logic
A system and method for controlling superconducting qubits is provided. In some aspects the method includes assembling, using a controller of a quantum computing system, a pulse subsequence that comprises pairs of voltage pulses timed symmetrically with respect to a period corresponding to a qubit frequency of a superconducting qubit in the quantum computing system. The method also includes generating, using the controller, a pulse sequence using a repetition of a pulse subsequence. The method further includes controlling the superconducting qubit by applying the pulse sequence to the superconducting qubit using a single flux quantum (SFQ) driver coupled thereto.
Compound superconducting quantum interference device output amplifier and methods
Output amplifier comprising a stack of compound superconducting quantum interference device (SQUID) output amplifier stages and related methods are provided. A method includes receiving a first pulse train comprising a first plurality of single flux quantum (SFQ) pulses. The method may further include receiving a second pulse train comprising a second plurality of SFQ pulses, where the second pulse train is delayed by a predetermined fraction of a clock cycle relative to the first pulse train. The method may further include using the stack of the plurality of compound SQUID output amplifier stages converting the first plurality of SFQ pulses and the second plurality of SFQ pulses into a voltage waveform, where each of the plurality of compound SQUID output amplifier stages comprises a pair of superconducting quantum interference devices (SQUIDs).