An image sensor includes a pixel sensor that senses an incident light and outputs a sampling signal of an analog shape, a sampler that compares the sampling signal and a ramp signal and outputs a comparison signal being time-axis length information, and a gray counter that counts a length of the comparison signal in synchronization with a clock signal and outputs a digital value. The gray counter includes a first flip-flop that divides the clock signal by 2 and generates a first gray code signal, a second flip-flop that delays a first data signal being a four-divided signal of the clock signal and outputs a second gray code signal, and a third flip-flop that delays the second gray code signal being two-divided and outputs a third gray code signal.

Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

A method performed by a first network entity (121, 131) for authenticating an event in a communications network (101, 102, 103, 104) is provided. The first network entity (121, 131) is configured to receive an event signal. The first network entity (121, 131) is also configured to authenticate the event if the received event signal correlates with an 5 output signal of a closed-loop shift register in the first network entity (121,131). Furthermore, the first network entity (121, 131) is configured to trigger a change in the closed-loop shift register in order to obtain a subsequent output signal from the closed-loop shift register. A first network entity (121, 131) for authenticating an event is also provided. Further, a wake-up receiver circuit (1210) comprising the first network entity 10 (121, 131) is provided, as well as, a wireless device (1200) comprising the wake-up receiver circuit (1210). Furthermore, a second network entity (110, 111, 112, 113) and a method therein for authenticating an event in at least one first network entity (121, 131) in a communications network (101, 102, 103, 104) are also provided. Also, a radio base station comprising the second network entity (110, 111, 112, 113) is provided, as well as, 15 computer programs and communications networks.

A method performed by a first network entity (121, 131) for authenticating an event in a communications network (101, 102, 103, 104) is provided. The first network entity (121, 131) is configured to receive an event signal. The first network entity (121, 131) is also configured to authenticate the event if the received event signal correlates with an 5 output signal of a closed-loop shift register in the first network entity (121,131). Furthermore, the first network entity (121, 131) is configured to trigger a change in the closed-loop shift register in order to obtain a subsequent output signal from the closed-loop shift register. A first network entity (121, 131) for authenticating an event is also provided. Further, a wake-up receiver circuit (1210) comprising the first network entity 10 (121, 131) is provided, as well as, a wireless device (1200) comprising the wake-up receiver circuit (1210). Furthermore, a second network entity (110, 111, 112, 113) and a method therein for authenticating an event in at least one first network entity (121, 131) in a communications network (101, 102, 103, 104) are also provided. Also, a radio base station comprising the second network entity (110, 111, 112, 113) is provided, as well as, 15 computer programs and communications networks.

An image sensor includes a pixel sensor that senses an incident light and outputs a sampling signal of an analog shape, a sampler that compares the sampling signal and a ramp signal and outputs a comparison signal being time-axis length information, and a gray counter that counts a length of the comparison signal in synchronization with a clock signal and outputs a digital value. The gray counter includes a first flip-flop that divides the clock signal by 2 and generates a first gray code signal, a second flip-flop that delays a first data signal being a four-divided signal of the clock signal and outputs a second gray code signal, and a third flip-flop that delays the second gray code signal being two-divided and outputs a third gray code signal.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system.

The embodiments of the present disclosure provide a data transmission circuit, a display device and a data transmission method. The data transmission circuit includes a serial-to-parallel conversion circuit configured to receive serial data and a mode setting signal, generate a mode selection signal according to the mode setting signal, and convert the serial data into parallel data with a corresponding bit width according to the mode selection signal; a control signal generating circuit configured to generate a control signal based on the mode setting signal; and a latch circuit connected to the serial-to-parallel conversion circuit and the control signal generating circuit, and being configured to receive the parallel data from the serial-to-parallel conversion circuit and the control signal from the control signal generating circuit, and latch and output the received parallel data under the control of the control signal.

The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC<3:0>, a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC<3:0> and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR<n:3>, and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR<n:3> and an upper bit latch signal 15.

The embodiments of the present disclosure provide a data transmission circuit, a display device and a data transmission method. The data transmission circuit includes a serial-to-parallel conversion circuit configured to receive serial data and a mode setting signal, generate a mode selection signal according to the mode setting signal, and convert the serial data into parallel data with a corresponding bit width according to the mode selection signal; a control signal generating circuit configured to generate a control signal based on the mode setting signal; and a latch circuit connected to the serial-to-parallel conversion circuit and the control signal generating circuit, and being configured to receive the parallel data from the serial-to-parallel conversion circuit and the control signal from the control signal generating circuit, and latch and output the received parallel data under the control of the control signal.