An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a first frequency divider arranged to receive the oscillating signal and output N frequency divided signals of different phases, a second frequency divider arranged to receive one of the N signals and frequency divide the received signal by a value given by a first control signal provided to the second frequency divider, N latch circuits each being arranged to receive a respective one of the N signals at a clocking input of the respective latch circuit and to receive an output of the second frequency divider at an input of the respective latch circuit, a multiplexer circuit arranged to receive outputs of the N latch circuits and to output a signal, on which the output signal is based, selected from the received signals based on a second control signal provided to the multiplexer circuit, and a control circuit arranged to provide the first control signal and the second control signal based on the divide ratio. A phase-locked loop circuit, a transceiver circuit, a radio station, and a method of frequency dividing an oscillating signal are also provided.

In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

A power converter having a clock module and a method for controlling a clock signal of the power converter. The clock module is configured to provide the clock signal and to set a clock frequency of the clock signal to a first predetermined frequency at the moment when the power converter is powered on. The clock module is further configured to regulate the clock frequency to increase from the first predetermined frequency to a second predetermined frequency through a predetermined times of step type frequency increase during a startup procedure of the power converter.

Embodiments of the present invention disclose a frequency divider and a radio communications device. The frequency divider includes a shift register unit and an output frequency synthesizing unit; the shift register unit includes multiple cyclically cascaded basic units; a basic unit at each level includes 2.sup.N D flip-flops connected in series and a multiplexer, outputs of the 2.sup.N D flip-flops connected in series are separately connected to the multiplexer; an output of the multiplexer is connected to an input of a next-level basic unit; the output frequency synthesizing unit superposes an output signal of the first D flip-flop of the basic unit at each level to generate a frequency division output signal.

A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2.sup.N-M1 times out of 2.sup.N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2.sup.N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2.sup.N-M, 2.sup.N-M times, using the divider.

An input value, where the input value is an amount which the current value of the counter is to be increased is received. The current value of the modulo binary counter and an offset value of the modulo binary counter are increased by the input value. Whether the current value of the counter is greater than or equal to the modulus value of the binary counter is determined. The current value of the counter is replaced with an updated offset value of the counter, where the updated offset value is the offset value of the counter increased by the input value. The updated offset value of the counter is returned.

The disclosure provides a multi-mode frequency division circuit including a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The divider performs frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator sequentially samples the frequency division clock signal according to the rising edge and falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and an indication signal.