A circuit device includes a control voltage input terminal to which a control voltage is inputted, an A/D conversion circuit A/D-converting the control voltage to generate control voltage data and A/D-converting a temperature detection voltage from a temperature sensor to generate temperature detection data, a processing circuit generating temperature compensation data of an oscillation frequency based on the temperature detection data and performing addition processing of the temperature compensation data and the control voltage data to generate frequency control data of the oscillation frequency, and an oscillation signal generation circuit generating an oscillation signal of the oscillation frequency set by the frequency control data, using the frequency control data and a resonator.

An oscillator includes a first container that includes a first base substrate and a first lid bonded to the first base substrate and has a first internal space, a second container that is accommodated in the first internal space and fixed to the first base substrate, a resonator element that is accommodated in the second container, a temperature sensor that is accommodated in the second container, a first circuit element that is accommodated in the second container and includes an oscillation circuit oscillating the resonator element and generating an oscillation signal on which temperature compensation is performed based on a detected temperature of the temperature sensor, and a second circuit element that is fixed to the first base substrate and includes a frequency control circuit that controls a frequency of the oscillation signal, in which the second container and the second circuit element are arranged side by side in plan view.

An oscillator includes a first container, a second container accommodated in the first container, a resonator element accommodated in the second container, a temperature sensor accommodated in the second container, a first circuit element that is accommodated in the second container and includes an oscillation circuit that causes the resonator element to oscillate so as to generate an oscillation signal on which temperature compensation is performed based on a detected temperature of the temperature sensor, and a second circuit element which is accommodated in the first container and includes a frequency control circuit that controls a frequency of the oscillation signal. The second container and the second circuit element are spaced from each other and are disposed to overlap each other in plan view.

An integrated circuit device includes a first temperature sensor, a second temperature sensor, an A/D conversion circuit that performs A/D conversion on first and second temperature detection voltages from the first and second temperature sensors and outputs first and second temperature detection data, a digital signal processing circuit that generates frequency control data by performing a temperature compensation process by a neural network calculation process based on the first and second temperature detection data, and an oscillation signal generation circuit that generates an oscillation signal of a frequency set by the frequency control data using a resonator.

Increases of circuit scale and power consumption are suppressed while frequency deviation is kept within a predetermined allowable range. A semiconductor device according to an embodiment includes a variable load capacity circuit including a plurality of load capacity elements coupled in parallel to one end of a crystal resonator and a plurality of switches that are respectively serially coupled to the load capacity elements, and a switch control unit that controls ON/OFF of the switches on the basis of information to be an index of frequency deviation due to temperature change of a frequency signal obtained by oscillating the crystal resonator. The switch control unit changes the number of switches that will be turned ON among the plurality of switches so that an absolute value of the frequency deviation becomes small when the information is not included in a predetermined allowable range.

Provided is a circuit device including: a phase comparison circuit that performs phase comparison between a reference clock signal and a feedback clock signal; a control voltage generation circuit that generates a control voltage; a voltage controlled oscillation circuit that generates a clock signal; a dividing circuit that divides the clock signal and outputs the feedback clock signal; a processing circuit that sets a division ratio of the dividing circuit; a first register in which slope information of a waveform signal for spreading the frequency of the clock signal is set; and a second register in which amplitude information of the waveform signal is set. The processing circuit generates a waveform signal value of the waveform signal based on the slope information and the amplitude information set in the first and second registers, and outputs division ratio data based on the waveform signal value and the division ratio setting value to the dividing circuit.

A circuit device includes a drive circuit driving a resonator, an oscillation circuit having the resonator and a variable capacitance circuit coupled to an oscillation loop including the drive circuit, and a D/A converter circuit that performs D/A conversion on frequency control data and outputs a first voltage signal and a second voltage signal which are differential signals. The variable capacitance circuit includes a first variable capacitance capacitor, to one end of which the first voltage signal is input and, to the other end of which a first bias voltage is input and a second variable capacitance capacitor, to one end of which the second voltage signal is input and, to the other end of which a second bias voltage is input.

Provided is a relaxation oscillator that is very small in temperature deviation of an oscillation period. The relaxation oscillator includes an oscillation circuit, a variable frequency divider, and a counter. The oscillation circuit is configured to switch between a first clock signal having a negative value as a first-order temperature coefficient of an oscillation period, and a second clock signal having a positive value as a first-order temperature coefficient of an oscillation period, based on a signal from the counter, and to output the switched-to clock signal as a third clock signal. The variable frequency divider is configured to divide the frequency of the third clock signal that is output from the oscillation circuit, and to output the frequency-divided third clock signal as a clock signal. The counter is reset by the clock signal.

Temperature-independent clock generation systems and methods are described that include a trained neural network coupled to a frequency correction circuit that corrects a crystal resonator output of a clock signal having a frequency that changes with changes in temperature. The neural network is trained with test temperatures and corresponding temperature based changes in frequency for test resonators of the same type as the resonator of the real time clock. The neutral network is trained to output frequency corrections based on a set of measured reference temperature-based changes in frequency for the crystal resonator and a current temperature of the resonator. The frequency correction circuit receives the frequency corrections from the neural network and corrects changes in the frequency caused by the changes in temperature of the resonator to provide a clock signal having an output frequency that is independent of the current temperature of the resonator.

In some aspects, the disclosure is directed to methods and systems for utilizing a thin-film bulk acoustic resonator (FBAR) as a frequency reference for a phase-locked loop (PLL) circuit controlling frequency of a voltage controlled oscillator (VCO). In some implementations, the FBAR-based oscillator may be used as a reference to an analog or digital PLL circuit (either directly, or divided to a lower frequency). In other implementations, the FBAR-based oscillator may be used as a reference to a mixing-based PLL rather than a dividing-based PLL. Through these implementations, the noise contribution of many of the PLL circuit components or elements may be reduced (e.g. noise from a delta-sigma modulator (DSM), multiple modulus divider (MMD), phase frequency detector (PFD)/charge pump (CP), etc.).