An oscillator circuit is provided. The oscillator circuit includes a first oscillator, a second oscillator, and a switch matrix. The first oscillator includes a first transconductance amplifier, a second transconductance amplifier, and a first resonator. The second oscillator includes a third transconductance amplifier, a fourth transconductance amplifier, and a second resonator. The first resonator includes a first capacitor element and a first inductor element. The second resonator includes a second capacitor element and a second inductor element. The first inductor element is coupled to the second inductor element. The switch matrix includes a first switch, a second switch, a third switch, and a fourth switch.

The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

A noise reduction system for a digital receiver reduces noise in signals received at the digital receiver. The digital receiver includes an input for receiving an analogue signal, analogue signal processing circuitry for processing an analogue signal, and an output for providing the processed signal to a digital signal processor. The noise reduction system is located between the input and the digital receiver input, and includes a first component that outputs results of a noise signal identification and a second component that applies one or more counter-measure to the received analogue signal to produce a modified analogue signal. The modified analogue signal has a reduced level of noise compared to the received analogue signal, wherein the noise reduction system is arranged to assess the effectiveness of the one or more counter-measures applied by the second component to determine whether any further counter-measures are required.

A noise reduction system for a digital receiver reduces noise in signals received at the digital receiver. The digital receiver includes an input for receiving an analogue signal, analogue signal processing circuitry for processing an analogue signal, and an output for providing the processed signal to a digital signal processor. The noise reduction system is located between the input and the digital receiver input, and includes a first component that outputs results of a noise signal identification and a second component that applies one or more counter-measure to the received analogue signal to produce a modified analogue signal. The modified analogue signal has a reduced level of noise compared to the received analogue signal, wherein the noise reduction system is arranged to assess the effectiveness of the one or more counter-measures applied by the second component to determine whether any further counter-measures are required.

A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator

In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.

A system and method for measuring power supply variations are described. A functional unit includes one or more power supply monitors capable of measuring power supply variations. The power supply monitors forego use of a clock signal from clock generating circuitry and forego use of a reference voltage from a reference power supply. The power supply monitors use an output of a source ring oscillator as a clock signal for the sequential elements of a counter. The counter measures a number of revolutions of a measuring ring oscillator within a period of the output of the source oscillator. The revolutions of the measuring ring oscillator are associated with a number of rising edges and falling edges of the output signal of the measuring ring oscillator. An encoder converts the output of the sequential elements to a binary value, and sends the binary value to an external age tracking unit.

Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.