Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

Techniques, systems and architectures for generating desired phase shifts in a phased array to control the directions of radiation in a wide range of angles are disclosed. Particularly, phased array architectures based on novel PLL-coupled phase shifting techniques for implementation in millimeter-wave (mm-wave) and sub-terahertz (sub-THz) operations range are described. In one aspect, a phased array including an array of unit cells is disclosed. In some embodiments, each unit cell in the array of unit cells includes a dual-nested PLL that is configured to effectuate phase locking and frequency locking to a reference signal from an adjacent unit cell. Moreover, each PLL includes control circuitry that can generate a wide range of phase shifts between adjacent unit cells to facilitate phased-array operations. Note that using the dual-nested PLL to generate a desired phase shift between adjacent radiating elements eliminates the use of conventional lossy phase shifters in the phased array.

Techniques are described herein that are capable of adjusting a center frequency of an adaptive voltage controlled oscillator (VCO) that is included in an adaptive phase lock loop (PLL) and/or a phase difference target of the adaptive PLL. An adaptive PLL is a PLL that includes an adaptive VCO. An adaptive VCO is a VCO that is capable of adjusting its center frequency and/or a phase difference target of the adaptive PLL that includes the adaptive VCO. The adaptive PLL may be configured to drive (e.g., control) a device. A drive signal that is used to drive the device and a resulting output signal that is proportional to movement of the device may be fed back to respective inputs of the adaptive PLL so that the phases of those signals may be processed to facilitate adjustment of the center frequency and/or the phase difference target.

A noise reduction system for a digital receiver reduces noise in signals received at the digital receiver. The digital receiver includes an input for receiving an analogue signal, analogue signal processing circuitry for processing an analogue signal, and an output for providing the processed signal to a digital signal processor. The noise reduction system is located between the input and the digital receiver input, and includes a first component that outputs results of a noise signal identification and a second component that applies one or more counter-measure to the received analogue signal to produce a modified analogue signal. The modified analogue signal has a reduced level of noise compared to the received analogue signal, wherein the noise reduction system is arranged to assess the effectiveness of the one or more counter-measures applied by the second component to determine whether any further counter-measures are required.

Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

A phase locking circuit includes: a phase comparator; a pulse generation circuit; a charge pump circuit; a loop filter circuit; and a voltage-controlled oscillator. The phase comparator samples a first level in synchronization with a received reference clock, and generates a first signal to be initialized to a second level that is different from the first level by using a feedback clock. The pulse generation circuit generates a second signal in accordance with the reference clock, and controls a phase of as output signal of the voltage-controlled oscillator to be the feedback clock to have a predetermined value by inputting the first signal and the second signal as a control voltage to the voltage-controlled oscillator through the charge pump circuit and the loop filter circuit.

Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO K.sub.DCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Techniques are described herein that are capable of adjusting a center frequency of an adaptive voltage controlled oscillator (VCO) that is included in an adaptive phase lock loop (PLL) and/or a phase difference target of the adaptive PLL. An adaptive PLL is a PLL that includes an adaptive VCO. An adaptive VCO is a VCO that is capable of adjusting its center frequency and/or a phase difference target of the adaptive PLL that includes the adaptive VCO. The adaptive PLL may be configured to drive (e.g., control) a device. A drive signal that is used to drive the device and a resulting output signal that is proportional to movement of the device may be fed back to respective inputs of the adaptive PLL so that the phases of those signals may be processed to facilitate adjustment of the center frequency and/or the phase difference target.

Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

An electronic device including a control circuit that receives a first signal from an external device and outputs a second signal based on the first signal, a phase locked loop circuit that outputs a first clock signal, a physical circuit that receives the first clock signal from the phase locked loop circuit and the second signal from the control circuit, and outputs a third signal based on the first clock signal and the second signal, and a driving circuit that outputs a transmit signal based on the third signal. The control circuit is operable in a high-speed mode and a low-power mode, and the control circuit powers off the phase locked loop circuit in the low-power mode and powers on the phase locked loop circuit in the high-speed mode.